NDLI: Novel One-Mask Self-Heating Pillar Phase Change Memory

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Advanced Dual Metal Gate MOSFETs with High-k Dielectric for CMOS Application

Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration

A 60nm NOR Flash Memory Cell Technology Utilizing Back Bias Assisted Band-to-Band Tunneling Induced Hot-Electron Injection (B4-Flash)

Fully 3-Dimensional NOR Flash Cell with Recessed Channel and Cylindrical Floating Gate - A Scaling Direction for 65nm and Beyond

A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond

Multi-Level NAND Flash Memory with 63 nm-Node TANOS (Si-Oxide-SiN-Al2O3-TaN) Cell Structure

A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates

Impact of Crystalline Phase of Ni-FUSI Gate Electrode on BTI and TDDB Reliability of HfSiON MOSFETs

Impact of Polarity and Hf concentration on Breakdown of HfSiON/SiO2 Gate Dielectrics

Newly Found Anomalous Gate Leakage Current (AGLC) for 65 nm Node and Beyond, and Its Countermeasure Using Nitrogen Implanted Poly-Si

Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

A Full FinFET DRAM Core Integration Technology Using a Simple Selective Fin Formation Technique

Vertex Channel Field Effect Transistor (VC-FET) Technology Featuring High Performance and Highly Manufacturable Trench Capacitor DRAM

Development of New TiN/ZrO2/Al2O3/ZrO2/TiN Capacitors Extendable to 45nm Generation DRAMs Replacing HfO2 Based Dielectrics

A 4-Bit Double SONOS Memory (DSM) with 4 Storage Nodes per Cell for Ultimate Multi-Bit Operation

A Novel Non-Volatile Memory Cell Using a Gated-Diode Structure with a Trapping-Nitride Storage Layer

Very Low Voltage SiO2/HfON/HfAlO/TaN Memory with Fast Speed and Good Retention

A Highly Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

A Novel Multi-Functional Silicon-On-ONO (SOONO) MOSFETs for SoC Applications: Electrical Characterization for High Performance Transistor and Embedded Memory Applications

Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

Performance Enhancement of MUGFET Devices Using Super Critical Strained-SOI (SC-SSOI) and CESL

Investigation of FinFET Devices for 32nm Technologies and Beyond

Strained N-Channel FinFETs with 25 nm Gate Length and Silicon-Carbon Source/Drain Regions for Performance Enhancement

Sub-5nm All-Around Gate FinFET for Ultimate Scaling

Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond

1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations

Scalable eSiGe S/D Technology with Less Layout Dependence for 45-nm Generation

50 nm Silicon-On-Insulator N-MOSFET Featuring Multiple Stressors: Silicon-Carbon Source/Drain Regions and Tensile Stress Silicon Nitride Liner

122 Mb High Speed SRAM Cell with 25 nm Gate Length Multi-Bridge-Channel MOSFET (MBCFET) on Bulk Si Substrate

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

TiN/HfSiOx Gate Stack Multi-Channel Field Effect Transistor (McFET) for Sub 55nm SRAM Application

Highly Reliable and Scalable Tungsten Polymetal Gate Process for Memory Devices Using Low-Temperature Plasma Selective Gate Reoxidation

Integration of Local Stress Techniques with Strained-Si Directly on Insulator (SSDOI) Substrates

Stress Memorization Technique (SMT) Optimization for 45nm CMOS

NiSi Schottky Barrier Process-Strained Si (SB-PSS) CMOS Technology for High Performance Applications

A Low Cost Drive Current Enhancement Technique Using Shallow Trench Isolation Induced Stress for 45-nm Node

Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage

SONOS-Type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory

Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window

Technology Breakthrough of Body-Tied FinFET for sub 50 nm NOR Flash Memory

Novel FUSI Strained Engineering for 45-nm Node CMOS Performance Enhancement

Dual Work Function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe Cap

Suppression Effects of Threshold Voltage Variation with Ni FUSI Gate Electrode for 45nm Node and Beyond LSTP and SRAM Devices

Demonstration of a New Approach Towards 0.25V Low-Vt CMOS Using Ni-Based FUSI

A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology

High Performance Micro-Crystallized TaN/SrTiO3/TaN Capacitors for Analog and RF Applications

Improved 1/f Noise Characteristics in Locally Strained Si CMOS Using Hydrogen-Controlled Stress Liners and Embedded SiGe

Impact of HfSiON Induced Flicker Noise on Scaling of Future Mixed-Signal CMOS

High-Performance Cu-Interconnects with Novel Seamless Low-k SiOCH Stacks (SEALS) Featured by Compositional Modulation Process for 45nm-Node ULSI Devices

Thermally and Chemically Robust, Non-Reflowable Low-k Spin-on Glass (k = 2.4) for Gap-Filling Technology in Sub-50-nm Memory Devices

Direct Non-Contact Electrical Measurement of Low-k Damage in Patterned Low-k Films by a Near-Field Scanned Microwave Probe

Integration of Self-Formed Barrier Technology for 32nm-Node Cu Dual-Damascene Interconnects with Hybrid Low-k (PAr/SiOC) Structure

Lower Resistance Scaled Metal Contacts to Silicide for Advanced CMOS

Highly Reliable 256Mb PRAM with Advanced Ring Contact Technology and Novel Encapsulating Technology

Novel One-Mask Self-Heating Pillar Phase Change Memory

A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications

World Smallest 0.34/spl mu/m~ COB Cell 1T1C 64Mb FRAM with New Sensing Architecture and Highly Reliable MOCVD PZT Integration Technology

High Density and High Reliability Chain FeRAM with Damage-Robust MOCVD-PZT Capacitor with SrRuO3/IrO2 Top Electrode for 64Mb and Beyond

Strain Controlled CMOSFET with Phase Controlled Full-Silicide (PC-FUSI)/HfSiON Gate Stack Structure for 45nm-node LSTP Devices

Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI)

Silicon-on-Insulator MOSFETs with Hybrid Crystal Orientations

25nm Short and Narrow Strained FDSOI with TiN/HfO2 Gate Stack

Pre-Metal Dielectric Stress Engineering by a Novel Plasma Treatment and Integration Scheme for nMOS Performance Improvement

A Novel Cu Electrical Fuse Structure and Blowing Scheme Utilizing Crack-Assisted Mode for 90-45nm-Node and Beyond

A New Route to Ultra-High Density Memory Using the Micro to Nano Addressing Block (MNAB)

The Features and Characteristics of 5-mega CMOS Image Sensor with Topologically Unique 1.7/spl m/m~1.7/spl mu/m Pixels

Strained-Si, Relaxed-Ge or Strained-(Si)Ge for Future Nanoscale p-MOSFETs?

Relationship Between Hole Mobility and Current Drive Enhancement in Uniaxially Strained Thin-Body SiGe-on-Insulator pMOSFETs

18.3 Superior Current Enhancement in SiGe Channel p-MOSFETs Fabricated on [110] Surface

Origin of Drivability Enhancement in Scaled pMOSFETs with 45/spl deg/ Rotated <100> Channels

High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology

Low Power CMOS Featuring Dual Work Function FUSI on HfSiON and 17ps Inverter Delay

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

55nm CMOS Technology for Low Standby Power/Generic Applications Deploying the Combination of Gate Work Function Control by HfSiON and Stress-Induced Mobility Enhancement

Poly-Si/AlN/HfSiO Stack for Ideal Threshold Voltage and Mobility in Sub-100 nm MOSFETs

Dual High-k Gate Dielectric Technology Using Selective AlOx Etch (SAE) Process with Nitrogen and Fluorine Incorporation

A Novel Remote Reactive Sink Layer Technique for the Control of N and O Concentrations in Metal/High-k Gate Stacks

Sub-1nm EOT HfSix/HfO2 Gate Stack Using Novel Si Extrusion Process for High Performance Application

Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions

RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology

Performance Enhancement in 45-nm Ni Fully-Silicided Gate/High-k CMIS Using Substrate Ion Implantation

Channel Stress Modulation and Pattern Loading Effect Minimization of Milli-Second Super Anneal for Sub-65nm High Performance SiGe CMOS

Novel Stack-SIN Gate Dielectrics for High Performance 30 nm CMOS for 45 nm Node with Uniaxial Strained Silicon

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

Two Different Mechanisms for Determining Effective Work Function (fm,eff) on High-k - Physical Understanding and Wider Tunability of fm,eff

Sub-1A-Resolution Analysis and Physical Understanding of Gate/Insulator Interfacial Region in Scaled-Tinv High-k Gate Stacks

Novel Approach to Reduce Source/Drain Series Resistance in High Performance CMOS Devices Using Self-Aligned CoWP Process for 45nm Node UTSOI Transistors with 20nm Gate Length

Advanced Junction Profile Engineering Featuring Laser Spike Annealing and Co-Implantation for Sub-30-nm Strained CMOS Devices

Unique Ultra Shallow Junction Scheme with Conventional Activation Process

A Raised Source/Drain Extension pFET on Si [110] Realized by In-situ Doped Selective Epitaxy Technology

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Novel One-Mask Self-Heating Pillar Phase Change Memory

Content Provider	IEEE Xplore Digital Library
Author	Happ, T.D. Breitwisch, M. Schrott, A. Philipp, J.B. Lee, M.H. Cheek, R. Nirschl, T. Lamorey, M. Ho, C.H. Chen, S.H. Chen, C.F. Joseph, E. Zaidi, S. Burr, G.W. Yee, B. Chen, Y.C. Raoux, S. Lung, H.L. Bergmann, R. Lam, C.
Copyright Year	2006
Description	Author affiliation: IBM Infineon Macronix PCRAM Joint Project, IBM Watson Res. Center, Yorktown Heights, NY (Happ, T.D.)
Abstract	A novel Pillar phase change memory based on fully integrated test arrays in 180nm CMOS technology has been successfully fabricated. A current-confining Pillar structure leads to a self-heating at the center of the chalcogenide layer, and needs only one additional mask level for its fabrication. Switching characteristics with write currents less than 900muA at 75nm diameter and multilevel operation are reported
Starting Page	120
Ending Page	121
File Size	779500
Page Count	2
File Format	PDF
ISBN	1424400058
DOI	10.1109/VLSIT.2006.1705246
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase change memory CMOS technology Phase change materials Phase change random access memory Electrodes Phased arrays CMOS process Contacts Tin Etching
Content Type	Text
Resource Type	Article

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