NDLI: Highly manufacturable and reliable 32 Mb FRAM technology with novel BC and capacitor cleaning process

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2015 Symposium on VLSI Technology (VLSI Technology)

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Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)

Proposal of system platform model. A semiconductor business model in the age of digital consumer products

Silicon technology-emerging trends from a system application perspective

Fermi level pinning at the polySi/metal oxide interface

The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond

Highly stable 65 nm node (CMOS5) 0.56 /spl mu/m/sup 2/ SRAM cell design for very low operation voltage

A 0.18 /spl mu/m logic-based MRAM technology for high performance nonvolatile memory applications

Fabrication of HfSiON gate dielectrics by plasma oxidation and nitridation, optimized for 65 nm mode low power CMOS applications

Design guideline of HfSiON gate dielectrics for 65 nm CMOS generation

Comparison of sub 1 nm TiN/HfO/sub 2/ with poly-Si/HfO/sub 2/ gate stacks using scaled chemical oxide interface

Novel plasma enhanced atomic layer deposition technology for high-k capacitor with EOT of 8 /spl Aring/ on conventional metal electrode

Design and proof of high quality HfAlO/sub x/ film formation for MOSCAPs and nMOSFETs through Layer-by-Layer Deposition and Annealing process

Novel multi-bit SONOS type flash memory using a high-k charge trapping layer

3D TFT-SONOS memory cell for ultra-high density file storage applications

Highly manufacturable SONOS non-volatile memory for the embedded SoC solution

Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric

Silicon nitride trap memory with double tunnel junction

The impact of oxynitride process, deuterium annealing and STI stress to1/f noise of 0.11 /spl mu/m CMOS

Low-K/Cu CMOS logic based SoC technology for 10 Gb transceiver with 115 GHz f/sub T/, 80 GHz f/sub MAX/ RF CMOS, high-Q MiM capacitor and spiral Cu inductor

Integration of 10 Gb/sec silicon lateral trench photodetector with high-performance CMOS

Local flare effects and correction in ArF lithography

ArF lithography technologies for 65 nm-node CMOS (CMOS5) with 30 nm logic gate and high density embedded memories

Cost-effective production using electron projection lithography for 65-nm node SoC and beyond

High performance 35 nm gate CMOSFETs with vertical scaling and total stress control for 65 nm technology

A new Si:C epitaxial channel nMOSFET architecture with improved drivability and short-channel characteristics

Improvement of threshold voltage roll-off by ultra-shallow junction formed by flash lamp annealing

Ultimate solution for low thermal budget gate spacer and etch stopper to retard short channel effect in sub-90 nm devices

Robust memory cell capacitor using multi-stack storage node for high performance in 90 nm technology and beyond

Technologies for scaling vertical transistor DRAM cells to 70 nm

Fin-Array-FET on bulk silicon for sub-100 nm trench capacitor DRAM

FBC (Floating Body Cell) for embedded DRAM on SOI

A functional 0.69 /spl mu/m/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform

Ultra-low power and high speed SRAM for mobile applications using single Poly-Si gate 90 nm CMOS technology

Robust process integration of 0.78 /spl mu/m/sup 2/ embedded SRAM with NiSi gate and low-K Cu interconnect for 90 nm SoC applications

Ultra low power 6T-SRAM chip with improved transistor performance and reliability by HfO/sub 2/-Al/sub 2/O/sub 3/ high-K gate dielectric process optimization

TiN/HfO/sub 2//TiN capacitor technology applicable to 70 nm generation DRAMs

A highly manufacturable 110 nm EDRAM process with Al/sub 2/O/sub 3/ stack MIM capacitor for cost effective high density, high speed, low voltage ASIC memory applications

HfO/sub 2/ and lanthanide-doped HfO/sub 2/ MIM capacitors for RF/mixed IC applications

Characterization and comparison of high-k metal-insulator-metal (MiM) capacitors in 0.13 /spl mu/m Cu BEOL for mixed-mode and RF applications

Thermally robust Ta-doped Ni SALICIDE process promising for sub-50 nm CMOSFETs

A 65 nm-node CMOS technology with highly reliable triple gate oxide suitable for power-considered system-on-a-chip

A high performance 90 nm logic technology with a 37 nm gate length, dual plasma nitrided gate dielectric and differential offset spacer

90 nm CMOS RF technology with 9.0 V I/O capability for single-chip radio

A novel self-aligned shallow trench isolation cell for 90 nm 4 Gbit NAND flash EEPROMs

Highly manufacturable 90 nm NOR flash technology with 0.081 /spl mu/m/sup 2/ cell size

New single-poly EEPROM with cell size down to 8F/sup 2/ for high density embedded nonvolatile memory applications

New buried bit-line NAND (BiNAND) Flash memory for data storage

(110)-surface strained-SOI CMOS devices with higher carrier mobility

Ultra-thin strained-SOI CMOS for high temperature operation

Strained silicon NMOS with nickel-silicide metal gate

Performance of 70 nm strained-silicon CMOS devices

Advanced 300 mm Cu/CVD LK (k=2.2) multilevel damascene integration for 90/65 nm generation BEOL interconnect technologies

Integration of Cu/low-k dual-damascene interconnects with a porous PAE/SiOC hybrid structure for 65 nm-node high performance eDRAM

High performance/reliability Cu interconnect with selective CoWP cap

Accurate modeling method for deep sub-micron Cu interconnect

Re-examination of subband structure engineering in ultra-short channel MOSFETs under ballistic carrier transport

Germanium MOS: an evaluation from carrier quantization and tunneling current

Very low defects and high performance Ge-on-insulator p-MOSFETs with Al/sub 2/O/sub 3/ gate dielectrics

Ge MOS characteristics with CVD HfO/sub 2/ gate dielectrics and TaN gate electrode

Novel CMP slurries for planarization of multilevel copper interconnect

Impacts of high modulus ultra low-k/Cu 300 mm-wafer integration for 65 nm technology node and beyond

Thermally robust 90 nm node Cu-Al wiring technology using solid phase reaction between Cu and Al

A HSQ-based inorganic sacrificial via filler-assisted 90 nm-node Cu/low-k OSG dual damascene process integration

High performance 25 nm FDSOI devices with extremely thin silicon channel

Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers

Strained FIP-SOI (finFET/FD/PD-SOI) for sub-65 nm CMOS scaling

Experimental evidence for the generation of bulk traps by negative bias temperature stress and their impact on the integrity of direct-tunneling gate dielectrics

Remote plasma-enhanced atomic layer deposition (RPEALD) nitride/oxide gate dielectric for sub-65 nm low standby power CMOS application

Low-energy nitrogen plasmas for 65-nm node oxynitride gate dielectrics: a correlation of plasma characteristics and device parameters

Impact of oxygen-enriched SiN interface on Al/sub 2/O/sub 3/ gate stack. An innovative solution to low-power CMOS

Highly manufacturable sub-50 nm high performance CMOSFET using real damascene gate process

A novel approach for integration of dual metal gate process using ultra thin aluminum nitride buffer layer

Robust HfN metal gate electrode for advanced MOS devices application

A novel NF/sub 3/-HDP-CVD process for STI-filling in sub-90 nm DRAM and beyond

The P-SOG filling Shallow Trench Isolation technology for sub-70 nm device

Novel Co/Ni bi-layer salicidation for 45 nm gate technology

Direct measurement of the inversion charge in MOSFETs: application to mobility extraction in alternative gate dielectrics

Energy distribution of interface traps in high-k gated MOSFETs

Dynamics of threshold voltage instability in stacked high-k dielectrics: role of the interfacial oxide

High mobility MISFET with low trapped charge in HfSiO films

Conventional poly-Si gate MOS-transistors with a novel, ultra-thin Hf-oxide layer

Highly manufacturable and reliable 32 Mb FRAM technology with novel BC and capacitor cleaning process

0.18 /spl mu/m SBT-based embedded FeRAM operating at a low voltage of 1.1 V

Full integration and reliability evaluation of phase-change RAM based on 0.24 /spl mu/m-CMOS technologies

An edge contact type cell for Phase Change RAM featuring very low power consumption

A novel cell technology using N-doped GeSbTe films for phase change RAM

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

1997 Symposium on VLSI Technology

1996 Symposium on VLSI Technology. Digest of Technical Papers

1995 Symposium on VLSI Technology. Digest of Technical Papers

Proceedings of 1994 VLSI Technology Symposium

Symposium 1993 on VLSI Technology

1992 Symposium on VLSI Technology Digest of Technical Papers

1991 Symposium on VLSI Technology

Digest of Technical Papers.1990 Symposium on VLSI Technology

1987 Symposium on VLSI Technology. Digest of Technical Papers

1986 Symposium on VLSI Technology. Digest of Technical Papers

1985 Symposium on VLSI Technology. Digest of Technical Papers

1984 Symposium on VLSI Technology. Digest of Technical Papers

1983 Symposium on VLSI Technology. Digest of Technical Papers

1982 Symposium on VLSI Technology. Digest of Technical Papers

1981 Symposium on VLSI Technology. Digest of Technical Papers

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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