NDLI: Deep sub-micron CMOS device design for low power analog applications

Please wait, while we are loading the content...

2015 Symposium on VLSI Technology (VLSI Technology)

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

2013 Symposium on VLSI Technology

2012 Symposium on VLSI Technology (VLSIT)

2011 Symposium on VLSI Technology - Digest of Technical Papers

2010 Symposium on VLSI Technology

2009 Symposium on VLSI Technology

2008 Symposium on VLSI Technology

2007 IEEE Symposium on VLSI Technology

2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

Manufacturing in the 21st century-new concept for 300 mm fab

Design technology for systems on a chip

Highly manufacturable and high performance SDR/DDR 4 Gb DRAM

Scaling towards 35 nm gate length CMOS

A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIs

Barrier-metal-free (BMF), Cu dual-damascene interconnects with Cu-epi-contacts buried in anti-diffusive, low-k organic film

High-quality ultra-thin HfO/sub 2/ gate dielectric MOSFETs with TaN electrode and nitridation surface preparation

Asymmetric source/drain extension transistor structure for high performance sub-50 nm gate length CMOS devices

Ultra-thin body PMOSFETs with selectively deposited Ge source/drain

Shallow n/sup +//p/sup +/ junction formation using plasma immersion ion implantation for CMOS technology

High performance sub-50 nm CMOS with advanced gate stack

A 0.115 /spl mu/m/sup 2/ 8F/sup 2/ DRAM working cell with LPRD (low parasitic resistance device) and poly metal gate technology for gigabit DRAM

A strategy for long data retention time of 512 Mb DRAM with 0.12 /spl mu/m design rule

A 0.15 /spl mu/m logic based embedded DRAM technology featuring 0.425 /spl mu/m/sup 2/ stacked cell using MIM (metal-insulator-metal) capacitor

W/WN/poly gate implementation for sub-130 nm vertical cell DRAM

A manufacturable 25 nm planar MOSFET technology

Experimental and simulation study on sub-50 nm CMOS design

High-performance 157 nm resist based on fluorine-containing polymer

Oxidation-resistant amorphous TaN barrier for MIM-Ta/sub 2/O/sub 5/ capacitors in giga-bit DRAMs

A heteroepitaxial MIM-Ta/sub 2/O/sub 5/ capacitor with enhanced dielectric constant for DRAMs of G-bit generation and beyond

Cylindrical Ru-SrTiO/sub 3/-Ru capacitor technology for 0.11 /spl mu/m generation DRAMs

Metal gate work function adjustment for future CMOS technology

Electrical characteristics of TaSi/sub x/N/sub y/ gate electrodes for dual gate Si-CMOS devices

Effects of high-/spl kappa/ dielectrics on the workfunctions of metal and silicon gates

Electron wavefunction penetration into gate dielectric and interface scattering-an alternative to surface roughness scattering model

Fabrication of a novel vertical pMOSFET with enhanced drive current and reduced short-channel effects and floating body effects

High performance 40 nm vertical MOSFET within a conventional CMOS process flow

Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding

Strained Si NMOSFETs for high performance CMOS technology

Ge-redistributed poly-Si/SiGe stack gate (GRPSG) for high-performance CMOSFETs

Performance improvement of metal gate CMOS technologies

Novel damage-free direct metal gate process using atomic layer deposition

Low resistivity bcc-Ta/TaN/sub x/ metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450/spl deg/C

50 nm SOI CMOS transistors with ultra shallow junction using laser annealing and pre-amorphization implantation

High performance sub-60 nm SOI MOSFETs with 1.2 nm thick nitride/oxide gate dielectric

Impact of CMOS process scaling and SOI on the soft error rates of logic processes

Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM

Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxide

A multi-gate dielectric technology using hydrogen pre-treatment for 100 nm generation system-on-a-chip

Controlling base-SiO/sub 2/ density of low-leakage 1.6 nm gate-SiON for high-performance and highly reliable n/pFETs

Radical nitridation in multi-oxide process for 100 nm generation CMOS technology

A 0.13-/spl mu/m SOI CMOS technology for low-power digital and RF applications

Deep sub-micron CMOS device design for low power analog applications

Investigations of bulk dynamic threshold-voltage MOSFET with 65 GHz "normal-mode" f/sub t/ and 220 GHz "over-drive mode" f/sub t/ for RF applications

A study of analog characteristics of CMOS with heavily nitrided NO oxynitrides

Transistor-limited constant voltage stress of gate dielectrics

Statistical analysis of soft breakdown in ultrathin gate oxides

A new quantitative hydrogen-based model for ultra-thin oxide breakdown

Gate voltage dependent model for TDDB lifetime prediction under direct tunneling regime

A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications

A high performance 0.12 /spl mu/m CMOS with manufacturable 0.18 /spl mu/m technology

High-density and high-performance 6T-SRAM for system-on-chip in 130 nm CMOS technology

Scalability and biasing strategy for CMOS with active well bias

Highly scalable sub-10F/sup 2/ 1T1C COB cell for high density FRAM

A fully planarized 8M bit ferroelectric RAM with 'chain' cell structure

A novel analysis method of threshold voltage shift due to detrap in a multi-level flash memory

New considerations for highly reliable PMOSFETs in 100 nm generation and beyond

Impact of low-standby-power device design on hot carrier reliability

Consistent model for short-channel nMOSFET post-hard-breakdown characteristics

Realization of high performance dual gate DRAMs without boron penetration by application of tetrachlorosilane silicon nitride films

Retention time improvement by fast-pull and fast-cool (FPFC) ingot growing combined with proper arrangement of subsequent thermal budget for 0.18 /spl mu/m DRAM cell and beyond

DRAM scaling-down to 0.1 /spl mu/m generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plug

A new storage node pad formation technology-line type SAC with oxide spacer (LSOS) and direct metal plug (DMP)-for 0.115 /spl mu/m tech and beyond

Dopant penetration effects on polysilicon gate HfO/sub 2/ MOSFET's

Performance and reliability of ultra thin CVD HfO/sub 2/ gate dielectrics with dual poly-Si gate electrodes

Ultra-thin ZrO/sub 2/ (or silicate) with high thermal stability for CMOS gate applications

MOS devices with high quality ultra thin CVD ZrO/sub 2/ gate dielectrics and self-aligned TaN and TaN/poly-Si gate electrodes

Optimization of annealing conditions for dual damascene Cu microstructures and via chain yields

Impact of vias on the thermal effect of deep sub-micron Cu/low-k interconnects

Scaling scenario of multi-level interconnects for future CMOS LSI

Non-uniform chip-temperature dependent signal integrity

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

1997 Symposium on VLSI Technology

1996 Symposium on VLSI Technology. Digest of Technical Papers

1995 Symposium on VLSI Technology. Digest of Technical Papers

Proceedings of 1994 VLSI Technology Symposium

Symposium 1993 on VLSI Technology

1992 Symposium on VLSI Technology Digest of Technical Papers

1991 Symposium on VLSI Technology

Digest of Technical Papers.1990 Symposium on VLSI Technology

1987 Symposium on VLSI Technology. Digest of Technical Papers

1986 Symposium on VLSI Technology. Digest of Technical Papers

1985 Symposium on VLSI Technology. Digest of Technical Papers

1984 Symposium on VLSI Technology. Digest of Technical Papers

1983 Symposium on VLSI Technology. Digest of Technical Papers

1982 Symposium on VLSI Technology. Digest of Technical Papers

1981 Symposium on VLSI Technology. Digest of Technical Papers

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in