NDLI: Direct measurement for SOI and bulk diodes of single-event-upset charge collection from energetic ions and alpha particles

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Push/Pull: PC technology/end user demand

Market and technology trends in the nomadic age

A Ti salicide process for 0.10 /spl mu/m gate length CMOS technology

Novel salicide technology using Ti hydrogenation for 0.1 /spl mu/m CMOS

25 /spl Aring/ gate oxide without boron penetration for 0.25 and 0.3-/spl mu/m PMOSFETs

Fully self-aligned 6F/sup 2/ cell technology for low cost 1Gb DRAM

A stack capacitor technology with (Ba,Sr)TiO/sub 3/ dielectrics and Pt electrodes for 1 Giga-Bit density DRAM

A new electrode technology for high-density nonvolatile ferroelectric (SrBi/sub 2/Ta/sub 2/O/sub 9/) memories

A 7.03-/spl mu/m/sup 2/ Vcc/2-plate nonvolatile DRAM cell with a Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etching

A comparative study of advanced MOSFET structures

High performance 0.15 /spl mu/m single gate Co salicide CMOS

High-performance double-layer epitaxial-channel PMOSFET compatible with a single gate CMOSFET

A gate-side air-gap structure (GAS) to reduce the parasitic capacitance in MOSFETs

A low temperature CVD Al plug and interconnect process for 0.25 /spl mu/m metallization technologies

Multilevel metallization based on Al CVD

A new CVD tungsten nitride diffusion barrier for Cu interconnection

Copper interconnection deposition techniques and integration

New erase scheme suitable for low power flash memory application

Optimum voltage scaling methodology for low voltage operation of CHE type flash EEPROMs with high reliability, maintaining the constant performance

Non-volatile FCG (ferroelectric-capacitor and transistor-gate connection) memory cell with non-destructive read-out operation

ROS: an extremely high density mask ROM technology based on vertical transistor cells

Channel engineering in sub-quarter-micron MOSFETs using nitrogen implantation for low voltage operation

Advanced ion implantation and rapid thermal annealing technologies for highly reliable 0.25 /spl mu/m dual gate CMOS

A 0.25 /spl mu/m gate length CMOS technology for 1V low power applications-device design and power/performance considerations

Single step PVD planarized aluminum interconnect with low-/spl epsiv/ organic ILD for high performance and low cost ULSI

Wide feature dielectric planarization using MnO/sub 2/ slurry

High-reliability interconnects using Cu-Zr alloy for future LSIs

Optimal low power interconnect networks

NURA: a feasible, gas-dielectric interconnect process

Manufacturable and reliable fluorine-doped low-k interlayer dielectric process for high performance logic LSI

An integrated low resistance aluminum plug and low-k polymer dielectric for high performance 0.25 /spl mu/m interconnects

A new two-step metal-CMP technique for a high performance multilevel interconnects featured by Al- and "Cu in low /spl epsiv/, organic film"-metallizations

Suppression of the SOI floating-body effects by linked-body device structure

Ultra-thin, highly uniform thin film SOI MOSFET with low series resistance using pattern-constrained epitaxy (PACE)

Suppression of threshold voltage variation in MTCMOS/SIMOX circuit operating below 0.5 V

Direct measurement for SOI and bulk diodes of single-event-upset charge collection from energetic ions and alpha particles

Asymmetrically-dope buried layer (ADB) structure CMOS for low-voltage mixed analog-digital applications

Silicon RF devices fabricated by ULSI processes featuring 0.1-/spl mu/m SOI-CMOS and suspended inductors

100-GHz f/sub T/ Si homojunction bipolar technology

A 50 GHz implanted base silicon bipolar technology with 35 GHz static frequency divider

Application of HSQ (hydrogen silsesquioxane) based SOG to pre-metal dielectric planarization in STC (stacked capacitor) DRAM

Highly reliable SiOF film formation by ECR-CVD using SiF/sub 2/H/sub 2/

Water re-absorption into hygroscopic film in interlayer dielectrics and its impact on hot-carrier immunity

A novel damascene process for one mask via/interconnect formation

History dependence of non-fully depleted (NFD) digital SOI circuits

Variable threshold-voltage SOI CMOSFETs with implanted back-gate electrodes for power-managed low-power and high-speed sub-1-V ULSIs

Data retention times in SOI-DRAMs

Design and performance of SOI pass transistors for 1 Gbit DRAMs

0.2 /spl mu/m analog CMOS with very low noise figure at 2 GHz operation

High performance CMOS for GHz communication IC

High-frequency characteristics and its dependence on parasitic components in 0.1 /spl mu/m Si-MOSFETs

Effects of quantization on the electrical characteristics of deep submicron p- and n-MOSFETs

A novel local interconnect technology (MSD) for high-performance logic LSIs with embedded SRAM

A symmetric diagonal driver transistor SRAM cell with imbalance suppression technology for stable low voltage operation

A 5-/spl mu/m/sup 2/ full-CMOS cell for high-speed SRAMs utilizing a optical-proximity-effect correction (OPC) technology

Impact of cosmic ray neutron induced soft errors on advanced submicron CMOS circuits

Electrical performances of retrograde versus conventional profile MOSFETs

Linear versus saturated drive current: tradeoffs in super steep retrograde well engineering

A shallow trench isolation study for 0.25/0.18 /spl mu/m CMOS technologies and beyond

An optimized densification of the filled oxide for quarter micron shallow trench isolation (STI)

Reverse short-channel effects and channel-engineering in deep-submicron MOSFETs: modeling and optimization

Two-stage drain leakage degradation in sub-micron MOSFET technology

Accurate determination of channel length, series resistance and junction doping profile for MOSFET optimisation in deep submicron technologies

Increase of parasitic resistance of shallow p+ extension with SiN sidewall process by hydrogen passivation of boron and its improvement by preamorphization for sub-0.25 /spl mu/m pMOSFETs

A high-performance 0.08 /spl mu/m CMOS

Plasma doping of boron for fabricating the surface channel sub-quarter micron PMOSFET

0.15 /spl mu/m delta-doped CMOS with on-field source/drain contacts

Ultra-shallow in-situ-doped raised source/drain structure for sub-tenth micron CMOS

Buried source and drain (BSD) structure for ultra-shallow junction using selective deposition of highly doped amorphous silicon

A low voltage graded-channel MOSFET (LV-GCMOS) for sub 1-volt microcontroller application

193 nm phase-shifting lithography with single layer resist for VLSIs beyond 1 G-bit DRAM

Fabrication of small contact with novel mask design

Feasibility demonstration of 0.18 /spl mu/m and 0.13 /spl mu/m optical projection lithography based on CD control calculations

Effects of ion energy distribution on topography dependent charging

An electromigration failure model of tungsten plug contacts/vias for realistic lifetime prediction

ESD design for deep submicron SOI technology [NMOS transistor]

The effect of intrinsic capacitance degradation on circuit performance

Random MOSFET parameter fluctuation limits to gigascale integration (GSI)

Gate oxide integrity (GOI) of MOS transistors with W/TiN stacked gate

Sub-quarter-micron dual gate CMOSFETs with ultra-thin gate oxide of 2 nm

Boron sidewall implantation and selective etching of p-doped poly-Si for 1 Gbit DRAM stacked capacitors

A manufacturable high performance quarter micron CMOS technology using I-line lithography and gate linewidth reduction etch process

Highly robust 0.25-/spl mu/m single-poly-gate CMOS with inter-well deep trenches

A manufacturable 0.30 /spl mu/m gate CMOS technology for high speed microprocessors

A high programming throughput 0.35 /spl mu/m p-channel DINOR flash memory

Effects of water vapor anneal on MIS devices made of nitrided gate dielectrics

The effect of nitrogen in p+ polysilicon gates on boron penetration into silicon substrate through the gate oxide

Direct lateral profiling of both interface traps and oxide charge in thin gate MOSFET devices

Mechanisms and characteristics of oxide charge detrapping in n-MOSFETs

A novel booster plate technology in high density NAND flash memories for voltage scaling-down and zero program disturbance

Impact of cell threshold voltage distribution in the array of flash memories on scaled and multilevel flash cell design

Read disturb degradation mechanism for source erase flash memories

Optimized HF solutions for ultra-clean Si surfaces

Process integration for the high speed NAND flash memory cell

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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