NDLI: Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations

Content Provider	IEEE Xplore Digital Library
Author	Mishra, K. Faraz, A. Singh, A.D. Chatterjee, A.
Copyright Year	2011
Abstract	One of the factors now beginning to seriously limit clock rates in large synchronous designs is manufacturing variations in device parameters. Moreover, such random process variations are increasing significantly with device scaling as technology approaches the end of the silicon roadmap. In a large design containing several millions of transistors, virtually every manufactured part will have a few hundreds of transistors that are significant performance outliers. Any one such device in a critical path can greatly limit the highest clock rate that can be achieved by the chip. In this paper we propose and analyze a new design approach that allows for the post manufacture tuning and speed-up of exceptionally slow circuit paths to recover much of the performance lost due to such outlier devices. We show that such tuning of exceptionally slow paths can result in a significant increase in the average clock speed attainable by the manufactured parts. We also show this method to be defect tolerant, implying an additional benefit of increasing the semiconductor yield.
Starting Page	382
Ending Page	388
File Size	438487
Page Count	7
File Format	PDF
ISBN	9781612843278
ISSN	10639667
DOI	10.1109/VLSID.2011.35
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-02
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transistors Tuning Delay Logic gates Performance evaluation Clocks Integrated circuit modeling clock rate Performance tuning path delay speed-up
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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