NDLI: Programmable Digital Frequency Multiplier

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Tutorial T1: Designing Secure SoCs

Tutorial T2: Organic Electronics: Technology, Devices, Circuits, and Applications

Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller

Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs

Tutorial T4B: Formal Assertion-Based Verification in Industrial Setting

Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends

Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations

Tutorial T7A: Advanced IC Packaging

Tutorial T7B: RF Analysis and Simulation with Focus on RF SiP Methodology

Tutorial T8A: Automated Application Engine Synthesis from C Algorithms

Tutorial T8B: Performance Debugging of Complex Embedded Systems

Tutorial IND1A: NeXperia - A Versatile Configurable Platform for Home and Mobile Computing

Tutorial IND1B: Realtime Operating Systems for Embedded Systems Development

Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA

Tutorial IND2B: Structured Embedded Configuration and Test

Creating a Culture of Innovation

Scaling, Power and the Future of CMOS

Nanoelectronics Device Technologies: CMOS, Beyond and the Mysterious Case of Ockham's Razor

Where Analog meets Digital and Beyond

Concurrent Optimization of Technology and Design for Nano CMOS

Reasoning about the Trends and Challenges of Engineering Design Automation

Nexperia Computing Architecture for Connected Consumer Applications

Convergence of Nanoelectronics and Living Cells: A New Frontier for Diagnostics and Therapy?

Systems, Nano-technology and SiP

Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions

Efficient Microprocessor Verification using Antecedent Conditioned Slicing

Synthesizing "Verification Aware" Models: Why and How?

Simulation Based Verification using Temporally Attributed Boolean Logic

Explicit Safety Property Strengthening in SAT-based Induction

Reusing Learned Information in SAT-based ATPG

A Process Scheduler-Based Approach to NoC Power Management

Analysis of RealTime Embedded Applications in the Presence of a Stochastic Fault Model

Online Dynamic Voltage Scaling using Task Graph Mapping Analysis for Multiprocessors

A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis

Architecting Microprocessor Components in 3D Design Space

Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits

FPGA Implementation of Low Power Parallel Multiplier

Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System

Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses

Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless Receiver

A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL

A 2 GHz Low Power Down-conversion Quadrature Mixer in 0.18-μm CMOS

A Low Power Frequency Multiplication Technique for ZigBee Transciever

7.95mW 2.4GHz Fully-Integrated CMOS Integer N Frequency Synthesizer

Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model

Design of Two-Stage Miller-Compensated Amplifiers Based on an Optimized Settling Model

A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling

Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design

Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation

Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective

Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis

Modeling and Analysis of Noise Margin in SET Logic

A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors

Compiler-Directed Code Restructuring for Operating with Compressed Arrays

Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings

Power Reduction in VLIW Processor with Compiler Driven Bypass Network

Customization of Register File Banking Architecture for Low Power

AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs

Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors

Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes

Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits

An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis

Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation

An ECO Technique for Removing Crosstalk Violations in Clock Networks

Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees

Bounded Delay Timing Analysis Using Boolean Satisfiability

A Novel CMOS Full Adder

Delay-Balanced Smart Repeaters for On-Chip Global Signaling

Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure

Design of A Fully Pipelined Single-Precision Multiply-Add-Fused Unit

Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors

Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques

Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs

Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding

Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms

Zero Cost Test Point Insertion Technique for Structured ASICs

Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs

Proposal of Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable Systems

Towards Generic On-the-Fly Reconfigurable Sensor Electronics for Embedded System- First Measurement Results of Reconfigurable Folded

Energy Driven Application SelfAdaptation

Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads

A Novel Approach to Domino Circuit Synthesis

Controllability-driven Power Virus Generation for Digital Circuits

Detection and Generation of Self-Timed Pipelines from High Level Specifications

A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures

Temperature-limited microprocessors: Measurements and design implications

On-Chip Voltage Down Converter Based on Moderate Inversion for Low- Power VLSI Chips

Statistical Leakage and Timing Optimization for Submicron Process Variation

Low Power Sensor Node for a Wireless Sensor Network

Power-Efficient Asynchronous Design

Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs

Model Based Test Generation for Microprocessor Architecture Validation

Spectral RTL Test Generation for Microprocessors

Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m)

Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST

A Reduced Complexity Algorithm for Minimizing N-Detect Tests

Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis

Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits

Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis

JouleQuest: An Accurate Power Model for the StarCore DSP Platform

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Modeling RTOS for Reactive Embedded Systems

On the Impact of Address Space Assignment on Performance in Systems-on-Chip

Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections

Application Specific Datapath Extension with Distributed I/O Functional Units

STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs

A 3-dimensional FEM Based Resistance Extraction

Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence

Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis

An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect

A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations

Power-efficient Instruction Encoding Optimization for Embedded Processors

Interpreting and Extending an Analytical Battery Model Using an Iterative Computation Method

Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM

An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function

LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability

Optimum Supply Voltages for Minimization of Leakage Currents in SRAM in Stand-by Mode

Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs

Low Power Pipelined TCAM Employing Mismatch Dependent Power Allocation Technique

Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips

Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI

Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors

A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology

Hardware Efficient Piecewise Linear Branch Predictor

A Neural Net Branch Predictor to Reduce Power

Embedded Support Vector Machine : Architectural Enhancements and Evaluation

Interframe Bus Encoding Technique for Low Power Video Compression

Process Variations and Process-Tolerant Design

Scalable techniques and tools for reliability analysis of large circuits

Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations

Impact of NBTI on FPGAs

On NBTI Degradation Process in Digital Logic Circuits

Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes

A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes

Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems

A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n)

A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems

Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing

Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan

Analog Circuit Testing Using Auto Regressive Moving Average Models

Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation

Modified Stability Checking for On-line Error Detection

Low Shift and Capture Power Scan Tests

Functional Broadside Tests with Different Levels of Reachability

Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture

Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform

A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance

An Enhanced CAM Architecture to Accelerate LZW Compression Algorithm

A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation

VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition

An Efficient Design of Cellular Automata Based Cryptographically Robust One-Way Function

SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition System

Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure

Parallelization of DC Analysis through Multiport Decomposition

Application of DC Analyzer to Combinatorial Optimization Problems

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects

A Placement Methodology for Robust Clocking

Calibration Based Methods for Substrate Modeling and Noise Analysis for Mixed-Signal SoCsc

Floorplanning in Modern FPGAs

Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization

Design and Testing of an Integrated Circuit for Multi-Electrode Neural Recording

A PMOS-diode Differential Body-driven Offset compensated 0.5V

Continuous Time Sigma Delta Modulator Employing a Novel Comparator Architecture

Programmable Digital Frequency Multiplier

On-chip implementation of a multi-output voltage regulator based on single inductor Buck Converter topology

A CMOS Low Voltage Charge Pump

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Programmable Digital Frequency Multiplier

Content Provider	IEEE Xplore Digital Library
Author	Wadhwa, S.K. Muhury, D. Thakur, K.
Copyright Year	2007
Description	Author affiliation: Freescale Semicond. India Pvt. Ltd., Noida (Wadhwa, S.K.; Muhury, D.; Thakur, K.)
Abstract	A programmable digital frequency multiplier with wide multiplication factor range and low lock time is presented. A digital algorithm is used to generate output frequency and an inbuilt PVT compensation mechanism ensures good frequency stability if there is any change in voltage and temperature during circuit operation. The circuit has been designed in 90 nm CMOS process for input reference frequency of 32.768 KHz and multiplication factor range of 128 to 1023. The silicon results show less than 2% of average frequency error at maximum multiplication factor.
Sponsorship	VLSI Soc. of India IEEE CAS Soc. IEEE ED Soc. ACM IEEE SSC Soc
Starting Page	925
Ending Page	928
File Size	365615
Page Count	4
File Format	PDF
ISBN	0769527620
ISSN	10639667
DOI	10.1109/VLSID.2007.133
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency Clocks Voltage Temperature Counting circuits Phase locked loops Silicon Circuit stability Equations Pulse generation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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