NDLI: Synthesizing "Verification Aware" Models: Why and How?

Content Provider	IEEE Xplore Digital Library
Author	Ganai, M.K. Mukaiyama, A. Gupta, A. Wakabayshi, K.
Copyright Year	2007
Description	Author affiliation: NEC Labs. America, Princeton, NJ (Ganai, M.K.)
Abstract	Design-for-verification (DFV) methodology i.e., exporting designer's intent to verification tools has been quite effective in improving verification efforts. The authors take one step further in improving the verification efforts, by separating the design optimized for performance, area and power from the design optimized for correctness, thereby reducing the verification burden. The authors propose a new paradigm synthesis-for-verification (SFV) which involves synthesizing "verification-aware" designs that are more suitable for functional verification. SFV methodology should be applied along with DFV methodology to obtain the full benefit of verification efforts. Note, this SFV paradigm requires support only from automated synthesis approaches, e.g. high level synthesis (HLS), and can be easily automated. This is in contrast to DFV methodology, which requires designers' reliable insights. As part of SFV methodology, the authors first identify the effect of various design entities on the performance of model checkers. By guiding the use of such entities in existing behavioral synthesis techniques, the authors propose to obtain "verification friendly" models that are relatively easier to model check. The authors demonstrate effectiveness of such a paradigm using existing industry tools and designs
Sponsorship	VLSI Soc. of India IEEE CAS Soc. IEEE ED Soc. ACM IEEE SSC Soc
Starting Page	50
Ending Page	56
File Size	530888
Page Count	7
File Format	PDF
ISBN	0769527620
ISSN	10639667
DOI	10.1109/VLSID.2007.151
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design optimization High level synthesis Design methodology National electric code Computer bugs Process design Bridges Scalability Power system modeling Laboratories
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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