NDLI: 20Gb/s 0.13/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer

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2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)

2004 Symposium on VLSI Circuits. Digest of Technical Papers - Title

Foreword - Welcome to the 2004 Symposium on VLSI Circuits

Executive Committees

Technical Program Committees

Table of contents

2004 VLSI Circuits Short Course Program

Session quick index

Session 1 - Plenary Session

Image processing chain in Digital Still Cameras

Semiconductor technologies support new generation hybrid car

Session 2 - RF Subsystems

An integrated 17 GHz front-end for ISM/WLAN applications in 0.13 /spl mu/m CMOS

A 72mW CMOS 802.11a direct conversion receiver with 3.5dB NF and 200kHz 1/f noise corner

An ultra-low power MEMS-based two-channel transceiver for wireless sensor networks

An injection locked, RF powered, telemetry IC in 0.25 /spl mu/m CMOS

Session 3 - Advanced High Data Rate DRAMs

Burst cycle data compression schemes for pre-fuse wafer-level test in large scale high-speed embedded DRAM

A 128Mb multi port media DRAM with four independent 4Gb/s serial ports

A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual clock input latch scheme and hybrid multi-oxide output buffer

Session 4 - Frequency Synthesizers and Oscillators

A /spl Sigma/-/spl Delta/ fractional-N synthesizer with a fully-integrated loop filter for a GSM/GPRS direct-conversion transceiver

A 4GHz Fractional-N synthesizer for IEEE 802.11a

Standing wave oscillators utilizing wave-adaptive tapered transmission lines

A 1.8 GHz LC VCO with 1.3 GHz tuning range and mixed-signal amplitude calibration

Session 5 - New FLASH and SRAM Developments

A 0.13-/spl mu/m, 0.78-/spl mu/m/sup 2/ low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme

Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement

A 0.9V 66MHz access, 0.13um 8M(256K/spl times/32) local SONOS embedded flash EEPROM

Self-boosted charge injection for 90-nm-node 4-Gb multilevel AG-AND flash memories programmable at 16 MB/s

Session 6 - Oversampling Converters

A calibration-free 3V 16b 500kS/s 6mW 0.5mm/sup 2/ ADC with 0.13 /spl mu/m CMOS

A third-order /spl Sigma//spl Delta/ modulator in 0.18 /spl mu/m CMOS with calibrated mixed-mode integrators

A 12 bit Continuous-Time /spl Sigma//spl Delta/ modulator with 400MHz clock and low jitter sensitivity in 0.13 /spl mu/m CMOS

A 3.3-V 240-MS/s CMOS bandpass /spl Sigma//spl Delta/ modulator using a fast-settling double-sampling SC filter

An 8MHz, 72 dB SFDR Asynchronous Sigma-Delta Modulator with 1.5mW power dissipation

Session 7 - On-Die Power Supply Integrity

Dynamic power-supply and well noise measurement and analysis for high frequency body-biased circuits

A built-in technique for probing power-supply noise distribution within large-scale digital integrated circuits

Circuits and techniques for high-resolution measurement of on-chip power supply noise

Power supply di/dt measurement using on-chip di/dt detector circuit

Development and validation of an electromagnetic distributed power grid model for the 90nm Pentium/spl reg/ 4 processor

Limitations of low FO4 designs

The future of embedded SRAM - cornerstone or millstone?

Analog CAD: computer aided design, or, computer accelerated disasters?

Session 8 - Plenary Session II

The World's Smallest RFID /spl mu/-Chip, bringing about new business and lifestyles

Fuel cells and portable electronics

Session 9 - Multi-Channel Transceivers

5-6.4 Gbps 12 channel transceiver with pre-emphasis and equalizer

A 1-4 Gbps quad transceiver cell using PLL with gate-current leakage compensator in 90nm CMOS

A 4-channel 3.125Gb/s/ch CMOS transceiver with 30dB equalization

Power analysis for high-speed I/O transmitters

Session 10 - Wireless Baseband

32 mW self contained OFDM receiver ASIC for mobile cellular applications

A CMOS 64MSps 20mA 0.85mm/sup 2/ baseband I/Q modulator performing 13 bits over 2MHz bandwidth

A COFDM baseband processor with robust synchronization for high-speed WLAN applications

An area-efficient implementation of digital-IF QAM coherent demodulator for software-defined radio receivers

Session 11 - Signal Processing

VLSI processor for reliable stereo matching based on window-parallel logic-in-memory architecture

A 2.8 Gb/s, 32-state, radix-4 Viterbi decoder add-compare-select unit

A 64-state 2GHz 500Mbps 40mW Viterbi accelerator in 90nm CMOS

A technique to build a secret key in integrated circuits for identification and authentication applications

Session 12 - New DRAM Cell Architectures and Design Techniques

SOI capacitor-less 1-transistor DRAM sensing scheme with automatic reference generation

2T1D memory cell with voltage gain

A 4.8-ns random access 144-Mb twin-cell-memory fabricated using 0.11-/spl mu/m cost-effective DRAM technology

A 130nm 1.1V 143MHz SRAM-like embedded DRAM COMPILER with Dual Asymmetric bit line Sensing Scheme and quiet unselected IO scheme

Session 13 - Multi Gb/s Serial Receivers

A 2Gbps and 7-multiplexing CDMA serial receiver chip for highly flexible robot control system

A 0.11 /spl mu/m CMOS clocked comparator for high-speed serial communications

A 10 Gb/s receiver with equalizer and on-chip ISI monitor in 0.11 /spl mu/m CMOS

A 2.5-V, 40-Gb/s decision circuit using SiGe BiCMOS logic

Session 14 - Analog Circuit Techniques

A pixel-parallel image processor for Gabor filtering based on merged analog/digital architecture

A low-power switched-current CDMA matched filter with on-chip V-I and I-V converters

An area-efficient, integrated, linear regulator with ultra-fast load regulation

A circuit design based approach for 1/f-noise reduction in linear analog CMOS IC's

Session 15 - Timing Generation

A 10+ GHz low jitter wide band PLL in 90 nm PD SOI CMOS technology

A 0.6-4.2V low-power configurable PLL architecture for 6 GHz-300 MHz applications in a 90 nm CMOS process

A background optimization method for PLL by measuring phase jitter performance

A sampling oscilloscope macro toward feedback physical design methodology

Session 16 - Digital Techniques I

Analysis and design of transceiver circuit and inductor layout for inductive inter-chip wireless superconnect

On-die CMOS leakage current sensor for measuring process variation in sub-90nm generations

High-resolution on-chip propagation delay detector for measuring within-chip and chip-to-chip variation

A 233MHz, 80-87% efficient, integrated, 4-phase DC-DC converter in 90nm CMOS

Session 17 - Serial Link Components

A six phases LC based ring oscillator for 1.5-3Gbit/s SATA interface

Burst mode packet receiver using a second order DLL

A 12.5Gbps half-rate CMOS CDR circuit for 10Gbps network applications

20Gb/s 0.13/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer

A 600MS/s, 5-bit pipelined analog-to-digital converter for serial-link applications

Session 18 - Low Power SRAM

64Mb mobile stacked single-crystal Si SRAM (S/sup 3/RAM) with selective dual pumping scheme (SDPS) and multi cell burn-in scheme (MCBS) for high density and low power SRAM

A 0.9ns random cycle 36Mb network SRAM with 33mW standby power

Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology

A transregional CMOS SRAM with single, logic V/sub DD/ and dynamic power rails

SRAM design on 65nm CMOS technology with integrated leakage reduction scheme

Session 19 - Sensor Microsystems

Pixel-level color image sensor with efficient ambient light suppression using modulated RGB flashlight and application to TOF range finding

A micro-sized photo detectable stimulator array for retinal prosthesis by distributed sensor network approach

CMOS monolithic atomic force microscope

A new input switching scheme for a capacitive micro-g accelerometer

A 2.2-mm/sup 2/ CMOS bioassay chip and wireless interface

Session 20 - Digital Techniques II

Design of high-speed and area-efficient Montgomery modular multiplier for RSA algorithm

Impact of body bias on alpha- and neutron-induced soft error rates of flip-flops

50Gb/s 3.3V logic ICs in InP-HBT technology

Energy-efficient low-voltage operation of digital CMOS circuits through charge-recycling

Microprocessor power optimization through multi-performance device insertion

Session 21- Adaptive Equalizers for Serial Communications

A quad multi-speed serializer/deserializer with analog adaptive equalization

A 3.125Gbps timing and data recovery front-end with adaptive equalization

Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver

Common-mode backchannel signaling system for differential high-speed links

Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 /spl mu/m CMOS

Session 22 - RF Circuit Techniques

A 1.2 volt 1.8GHz CMOS quadrature front-end

A 15-GHz integrated CMOS switch with 21.5-dBm IP/sub 1dB/ and 1.8-dB insertion loss

A circuit technique improving the image rejection of RF front-ends

Low-power 5 GHz LNA and VCO in 90 nm RF CMOS

Accurate subcircuit model of an on-chip inductor with a new substrate network

Session 23 - Digital Building Blocks

A dynamic CAM - based on a one-hot-spot block code - for millions-entry lookup

A 90nm 6.5GHz 128/spl times/64b 4-read 4-write ported parameter variation tolerant register file

An automatic direction control scheme for bi-directional bus repeaters with dynamic collaborative driving

A 16Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling

A mixed signal rotator/shifter for 8GHz Intel/spl reg/ Pentium/spl reg/ 4 integer core

Session 24 - Optical Communication Components

Notice of Violation of IEEE Publication Principles A low voltage 10Gbps SiGe laser diode driver using adaptive RC compensation and common-mode feedback based current generators

Notice of Violation of IEEE Publication Principles A 10Gb/s SiGe transimpedance amplifier using a pseudo-differential input stage and a modified Cherry-Hooper amplifier

A 20mW 85dB/spl Omega/ 1.25Gb/s CMOS transimpedance amplifier with photodiode capacitance cancellation

CMOS transceiver with baud rate clock recovery for optical interconnects

A 1.25Gbit/s CMOS burst-mode optical transceiver for Ethernet PON system

Session 25 - Nyquist AID Converters

A 4GS/s 6b flash ADC in 0.13 /spl mu/m CMOS

A 600 MSPS 8-bit folding ADC in 0.18 /spl mu/m CMOS

A highly integrated analog baseband transceiver featuring a 12-bit 180MSPS pipelined A/D converter for multi-channel wireless LAN

A 1.5-V 10-b 50 MS/s time-interleaved switched-opamp pipeline CMOS ADC with high energy efficiency

0.9V 12mW 2MSPS algorithmic ADC with 81dB SFDR

Session 26 - Emerging Non-Volatile Memories

An 8Mb demonstrator for high-density 1.8V Phase-Change Memories

High density and low power nonvolatile FeRAM with non-driven plate and selected driven bit-line scheme

A voltage-dependent switching-time (VDST) model of ferroelectric capacitors for low-voltage FeRAM circuits

A 1.2V 1Mbit embedded MRAM core with folded bit-line array architecture

A 16Mb MRAM featuring bootstrapped write drivers

[Inside back cover - blank]

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

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20Gb/s 0.13/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer

Content Provider	IEEE Xplore Digital Library
Author	Chiang, P. Dally, W.J. Lee, M.-J.E. Senthinathan, R. Yangjin Oh Horowitz, M.
Copyright Year	2003
Description	Author affiliation: Stanford Univ., CA, USA (Chiang, P.; Dally, W.J.)
Abstract	A 20Gb/s transmitter is implemented in 0.13/spl mu/m CMOS technology. Eight 2.5Gb/s data streams are 4:1 multiplexed, sampled, and retimed into two 10Gb/s data streams. A final 20Gb/s 2:1 output multiplexer, clocked by complementary phases of an LC-VCO (voltage controlled oscillator) in a phase-locked loop, creates 20Gb/s data. The VCO is integrated with the output multiplexer, resonating the load and eliminating the need for clock buffers. Power, active die area, and jitter (RMS/pk-pk) are 165mW, 650/spl mu/m /spl times/ 350/spl mu/m, and 2.37ps/15ps, respectively.
Starting Page	272
Ending Page	275
File Size	357240
Page Count	4
File Format	PDF
ISBN	0780382870
DOI	10.1109/VLSIC.2004.1346584
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transmitters Multiplexing Jitter Clocks Phase locked loops Bandwidth Timing Voltage-controlled oscillators CMOS technology Circuits
Content Type	Text
Resource Type	Article

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