NDLI: Near speed-of-light on-chip electrical interconnect

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The evolution of monolithic and polylithic interconnect technology

Ultralow-power CMOS/SOI LSI design for future mobile systems

Power dissipation issues in interconnect performance optimization for sub-180 nm designs

A transition-encoded dynamic bus technique for high-performance interconnects

Near speed-of-light on-chip electrical interconnect

Bending-comb capacitor with a small parasitic inductance

Analog front end IC for 3G WCDMA

A 125 MHz-86 dB IM3 programmable-gain amplifier

A monolithic CMOS 10.4-GHz phase locked loop

An integrated mixed-signal front-end for broadband modems

Programmable and automatically-adjustable sense-amplifier activation scheme and multi-reset address-driven decoding scheme for high-speed reusable SRAM core

90% write power saving SRAM using sense-amplifying memory cell

A 4.5 GHz 130 nm 32 KB L0 cache with a self reverse bias scheme

A 6 GHz, 16 Kbytes L1 cache in a 100 nm dual-V/sub T/ technology using a bitline leakage reduction (BLR) technique

An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes

1.2 Gbps/pin simultaneous bidirectional transceiver logic with bit deskew technique

1.5 Gbps, 5150 ppm spread spectrum SerDes PHY with a 0.3 mW, 1.5 Gbps level detector for serial ATA

A 0.13-/spl mu/m CMOS 5-Gb/s 10-meter 28 AWG cable transceiver with no-feedback-loop continuous-time post-equalizer

Four-way processor 800 MT/s front side bus with ground referenced voltage source I/O

Programmable termination for CML I/O's in high speed CMOS transceivers

High performance SRAMs in 1.5 V, 0.18 /spl mu/m partially depleted SOI technology

Static pulsed bus for on-chip interconnects

A 5 Gbps CMOS frequency tolerant multi phase clock recovery circuit

A 1.6 Gb/s, 3 mW CMOS receiver for optical communication

A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

A 1.2 Gbps CMOS DFE receiver with the extended sampling time window for application to the SSTL channel

Technology trends of high-definition digital still camera systems

Wireless implantable microsystems: coming breakthroughs in health care

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

A 110 nm 512 Mb DDR DRAM with vertical transistor trench cell

A low-noise 2-GB/s 256-Mb packet-based DRAM with a robust array power supply

1-Gb/s/pin multi-gigabit DRAM design with low impedance hierarchical I/O architecture

SOI-optimized 64-bit high-speed CMOS adder design

A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core

Designing a 3 GHz, 130 nm, Intel/sup /spl reg// Pentium/sup /spl reg// 4 processor

A 380-MHz CMOS linear-in-dB signal-summing variable gain amplifier with gain compensation techniques for CDMA systems

A 1-V 3.5-mW CMOS switched-opamp quadrature IF circuitry for Bluetooth receivers

A 1.8 V digital A/D converter in 0.18 /spl mu/m CMOS

A 16 b quadrature direct digital frequency synthesizer using interpolative angle rotation algorithm

A robust array architecture for a capacitorless MISS tunnel-diode memory

SESO memory: a CMOS compatible high density embedded memory technology for mobile applications

MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current

A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects

Enabling high-performance mixed-signal system-on-a-chip (SoC) in high performance logic CMOS technology

/spl mu/I/O architecture for 0.13-/spl mu/m wide-voltage-range system-on-a-package (SoP) designs

0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array-voltage scheme

A 2.9ns random access cycle embedded DRAM with a destructive-read

A low power 200 MHz receiver for wireless hearing aid devices

A 6.5 GHz CMOS FSK modulator for wireless sensor applications

A 40 GHz VCO with 9 to 15% tuning range in 0.13 /spl mu/m SOI CMOS

A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-/spl mu/m CMOS process

Ferroelectric-based functional pass-gate for low-power VLSI

Ferroelectric memory based secure dynamically programmable gate array

Selective node engineering for chip-level soft error rate improvement [in CMOS]

Threshold-voltage balance for minimum supply operation

Crosstalk delay analysis of a 0.13-/spl mu/m-node test chip and precise gate-level simulation technology

Design rule for frequency-voltage cooperative power control and its application to an MPEG-4 decoder

Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing

Design and validation of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors power delivery

A 2.17 dB NF, 5 GHz band monolithic CMOS LNA with 10 mW DC power consumption

A 1.8-V operation RFCMOS transceiver for Bluetooth

A 17 mW transmitter and frequency synthesizer for 900 MHz GSM fully integrated in 0.35-/spl mu/m CMOS

A CMOS single-chip direct conversion satellite receiver for digital broadcasting system

A general-purpose vector-quantization processor employing two-dimensional bit-propagating winner-take-all

A 400-MHz processor for the efficient conversion of rectangular to polar coordinates for digital communications applications

Fully-parallel pattern-matching engine with dynamic adaptability to Hamming or Manhattan distance

A 500 MHz 50 mW Viterbi detector for DVD systems using simplified ACS and new path memory architecture

A still image encoder based on adaptive resolution vector quantization realizing compression ratio over 1/200 featuring needless calculation elimination architecture

A new architecture of programmable digital vision chip

A binocular CMOS range image sensor with bit-serial block-parallel interface using cyclic pipelined ADCs

An advanced fingerprint sensor LSI and its application to a fingerprint identification system

An on-chip high-efficiency DC-DC converter with a compact timing edge control circuit

SOI circuit technology for batteryless mobile system with green energy sources

Multi-mode CMOS low dropout voltage regulator for GSM handsets

High efficiency and latch-up free switched capacitor up converter on FD-SOI technology

Double boosting pump, hybrid current sense amplifier, and binary weighted temperature sensor adjustment schemes for 1.8V 128Mb mobile DRAMs

A differential-capacitance read scheme for FeRAMs

Constant-charge-injection programming for 10-MB/s multilevel AG-AND flash memories

A 125MHz burst mode 0.18/spl mu/m 128Mbit 2 bits per cell flash memory

Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors

Forward body bias for microprocessors in 130nm technology generation and beyond

Leakage-biased domino circuits for dynamic fine-grain leakage reduction

A leakage-tolerant dynamic register file using leakage bypass with stack forcing (LBSF) and source follower NMOS (SFN) techniques

A 6bit 400Msps 70mW ADC using interpolated parallel scheme

A 1.2 V 10-b 100-MSamples/s A/D converter in 0.12/spl mu/m CMOS

A floating-gate trimmed, 14-bit, 250 Ms/s digital-to-analog converter in standard 0.25 /spl mu/m CMOS

A 4th-order local-feedforward D/A converter that prevents limit-cycle oscillation

Dual supply voltage clocking for 5 GHz 130 nm integer execution core

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

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1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)

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Near speed-of-light on-chip electrical interconnect

Content Provider	IEEE Xplore Digital Library
Author	Chang, R.T. Yue, C.P. Wong, S.S.
Copyright Year	2002
Description	Author affiliation: Center for Integrated Syst., Stanford Univ., CA, USA (Chang, R.T.; Yue, C.P.; Wong, S.S.)
Abstract	The propagation limits of electrical signals for systems built with conventional silicon processing are explored. Data transmission near the speed of light with an all-electrical system can be achieved by taking advantage of the inductance-dominated high-frequency regime of on-chip interconnect. In a 0.18 /spl mu/m, 6-level Aluminum CMOS technology, an overall delay of 278 ps for a 20 mm long line corresponding to a propagation velocity of one half the speed of light in silicon dioxide has been demonstrated.
Starting Page	18
Ending Page	21
File Size	235126
Page Count	4
File Format	PDF
ISBN	0780373103
DOI	10.1109/VLSIC.2002.1015032
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency Wire Repeaters Optical propagation Silicon Aluminum CMOS technology Propagation delay Integrated circuit interconnections Power system interconnection
Content Type	Text
Resource Type	Article

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