NDLI: Design and characterization of vertical mesh capacitors in standard CMOS

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2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

Digital vision chips and high-speed vision systems

BSIM model for circuit design using advanced technologies

Full-CMOS 2.4 GHz wideband CDMA transmitter and receiver with direct conversion mixers and DC-offset cancellation

Single-chip IF transceiver IC with wide dynamic range variable gain amplifiers for wideband CDMA applications

A 0 dB-IL, 2140/spl plusmn/30 MHz bandpass filter utilizing Q-enhanced spiral inductors in standard CMOS

A 2 GHz merged CMOS LNA and mixer for WCDMA

Robustness of sub-70 nm dynamic circuits: analytical techniques and scaling trends

A 0.13 /spl mu/m 6 GHz 256/spl times/32b leakage-tolerant register file

480 ps 64-bit race logic adder

A conditional keeper technique for sub-0.13/spl mu/ wide dynamic gates

A cell transistor scalable array architecture for high-density DRAMs

Bit line coupling scheme and electrical fuse circuit for reliable operation of high density DRAM

An area-efficient 2 GB/s 256 Mb packet-based DRAM with daisy-chained redundancy scheme

A 66-400 MHz, adaptive-lock-mode DLL circuit with duty-cycle error correction [for SDRAMs]

A stabilization technique for phase-locked frequency synthesizers

A fully-integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

1-GHz and 2.8-GHz CMOS injection-locked ring oscillator prescalers

Automatic calibration of modulated /spl Sigma/-/spl Delta/ frequency synthesizers

Autonomous decentralized low-power system LSI using self-instructing predictive shutdown method

ASIC design methodology with on-demand library generation

Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 /spl mu/

Single-electron pass-transistor logic and its application to a binary adder

A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs

A new column redundancy scheme for yield improvement of high speed DRAMs with multiple bit pre-fetch structure

A system LSI memory redundancy technique using an ie-Flash (inverse-gate-electrode flash) programming circuit

A 50-MHz 98-dB dynamic-range dB-linear programmable-gain amplifier with 2-dB gain steps for 3-V power supply

A temperature stable CMOS variable gain amplifier with 80-dB linearly controlled gain range

A variable gain IF amplifier with -67 dBc IM/sub 3/-distortion at 1.4 V/sub pp/ output in 0.25 /spl mu/m CMOS

Development trends of LTPS TFT LCDs for mobile applications

Electronics for DLP/sup TM/ technology based projection systems

A 120 mW embedded 3D graphics rendering engine with 6 Mb logically local frame-buffer and 3.2 GByte/s run-time reconfigurable bus for PDA-chip

Low power motion compensation block IP with embedded DRAM macro for portable multimedia applications

Dynamically reconfigurable logic LSI-PCA-1

A 1 GHz power efficient single chip multiprocessor system for broadband networking applications

A 1.57 GHz fully integrated very low phase noise quadrature VCO

An optimally coupled 5 GHz quadrature LC oscillator

A highly-tunable 12 GHz quadrature LC-VCO in SiGe BiCMOS process

A 1.8 GHz CMOS VCO with reduced phase noise

A novel sensing scheme for an MRAM with a 5% MR ratio

A pulse-tuned charge controlling scheme for uniform main and reference bitline voltage generation on ITIC FeRAM

A bit-line GND sense technique for low-voltage operation FeRAM

A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM

An efficient digital sliding controller for adaptive power supply regulation

A 1.8 V single-inductor dual-output switching converter for power reduction techniques

A 0.6-V voltage reference circuit based on /spl Sigma/-V/sub TH/ architecture in CMOS/SIMOX

Sub-1 V process-compensated MOS current generation without voltage reference

A single-chip 12.5 Gbaud transceiver for serial data communication

An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications

An SOI CMOS LVDS driver and receiver pair

A 15-GHz wireless interconnect implemented in a 0.18-/spl mu/m CMOS technology using integrated transmitters, receivers, and antennas

Effects of power-supply parasitic components on substrate noise generation in large-scale digital circuits

Parametric yield enhancement system via circuit level device optimization using statistical circuit simulation

A floating-body charge monitor circuit for partially depleted SOI CMOS

A pixel-level automatic calibration circuit scheme for sensing initialization of a capacitive fingerprint sensor LSI

A 200 MHz 7th-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25 /spl mu/m CMOS process

A micropower log-domain filter using enhanced lateral PNPs in a 0.25 /spl mu/m CMOS process

A low-swing clock double-edge triggered flip-flop

On-die clock jitter detector for high speed microprocessors

P-boosted source followers: a robust energy-efficient bus driver technique

Two schemes to reduce interconnect delay in bi-directional and uni-directional buses

Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling

Silicon integrated high performance inductors in a 0.18 /spl mu/m CMOS technology for MMIC

Design and characterization of vertical mesh capacitors in standard CMOS

A JTAG based AC leakage self-test

A 1 V operational, 20 MS/s and 57 dB of S/N, current-mode CMOS sample-and-hold IC

An 8-bit 30 MS/s 18 mW ADC with 1.8 V single power supply

A 12-bit mismatch-shaped pipeline A/D converter

An 8-GHz bandwidth 1-GS/s GaAs HBT dual track-and-hold

Comparative performance, leakage power and switching power of circuits in 150 nm PD-SOI and bulk technologies including impact of SOI history effect

A 0.5 V power-supply scheme for low power LSIs using multi-Vt SOI CMOS technology

A 0.9-/spl mu/A standby current DSP core using improved ABC-MT-CMOS with charge pump circuit

A 63 /spl mu/W-standby-power microcontroller with on-chip hybrid regulator scheme

Quasi-worst-condition built-in-self-test scheme for 4-Mb loadless CMOS four-transistor SRAM macro

A 800 MHz single cycle access 32 entry fully associative TLB with a 240 ps access match circuit

A reconfigurable multilevel parallel graphics cache memory with 75 GB/s parallel cache replacement bandwidth

A 6.25 ns random access 0.25 /spl mu/m embedded DRAM

A fully-integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

A single-chip 2.4 GHz direct-conversion CMOS transceiver with GFSK modem for Bluetooth application

Concurrent dual-band CMOS low noise amplifiers and receiver architectures

Fully integrated 2.2 mW CMOS front-end for a 900 MHz zero-IF wireless receiver

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)

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Digest of Technical Papers., Symposium on VLSI Circuits.

Proceedings of 1994 IEEE Symposium on VLSI Circuits

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Symposium 1988 on VLSI Circuits

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