NDLI: Embedded DRAM for a reconfigurable array

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2015 Symposium on VLSI Circuits (VLSI Circuits)

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Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

Semiconductor industry evolution for 21/sup st/ century

CMOS technology: Present and future

A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization

A 1 V, 10.4 mW low power DSP core for mobile wireless use

A compact 54/spl times/54-bit multiplier with improved Wallace-tree structure

A 250 MHz CMOS floating-point divider with operand pre-scaling

A 50 Gb/s 32/spl times/32 CMOS crossbar chip using asymmetric serial links

840 Mb/s CMOS demultiplexed equalizing transceiver for DRAM-to-processer communication

A low-power multi-gigabit CMOS/SIMOX LSI design using two power supply voltages

A 3.6 Gb/s 340 mW 16:1 pipe-lined multiplexer using SOI-CMOS technology

Charge sharing concept for power efficiency and EME improvement of boosted charge pumps in NVMs

A sampling weak-program method to tighten Vth-distribution of 0.5 V for low-voltage flash memories

A source-line programming scheme for low voltage operation NAND flash memories

A 144 Mb 8-level NAND flash memory with optimized pulse width programming

A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver

An integratable 1-2.5 Gbps low jitter CMOS transceiver with built in self test capability

A 1 Gbps transceiver with receiver-end deskewing capability using non-uniform tracked oversampling and a 250-750 MHz four-phase DLL

GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link

Wide tuning range inversion-mode gated varactor and its application on a 2-GHz VCO

1.5 V 10-12.5 GHz integrated CMOS oscillators

On-chip active guard band filters to suppress substrate-coupling noise in analog and digital mixed-signal integrated circuits

A high-voltage output buffer fabricated on a 2 V CMOS technology

1999 vlsi circuits symposium rump sessions

10-100 Gb/s throughput CMOS techniques

Technical trends of LSI packaging: recent advances in CSPs and high density substrates

A 10 b, 400 MS/s glitch-free CMOS D/A converter

An 8 b 500 MS/s full Nyquist cascade A/D converter

A 1 V 6 b 50 MHz current-interpolating CMOS ADC

An 8 b 100 MSample/s CMOS pipelined folding ADC

CMOS 10 MHz-IF downconverter with on-chip broadband circuit for large image-suppression

A 12.4 mW CMOS front-end for a 5 GHz wireless-LAN receiver

A wideband bandpass sigma-delta modulator for wireless applications

A delta-sigma true RMS-to-DC converter using an indirect-charge-transfer filter

High-speed cascode sensing scheme for 1.0 V contact-programming mask ROM

A 3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme

A robust 8F/sup 2/ ferroelectric RAM cell with depletion device (DeFeRAM)

Gain cell block architecture for gigabit-scale chain ferroelectric RAM

A 500 MHz, write-bypassed, 88-entry, 90-bit register file

A 1.0 ns access 770 MHz 36 Kb SRAM macro

A 550-ps access, 900-MHz, 1-Mb ECL-CMOS SRAM

A 5 GHz, 32 mW CMOS frequency synthesizer with an injection locked frequency divider

A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-/spl mu/m CMOS technology

A 2 V 150 MHz CMOS digital phase modulator for fast-switching frequency synthesis

A Precharged-Capacitor-Assisted Sensing (PCAS) scheme with novel level controller for low power DRAMs

A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4 Gb DRAM's

A pseudo multi-bank DRAM with categorized access sequence

A DRAM system for consistently reducing CPU wait cycles

100.000 pixel 120 dB imager in TFA-technology

A high speed, 500 frames/s, 1024/spl times/1024 CMOS active pixel sensor

A CMOS imager with new focal-plane motion detectors

A smart CMOS imager with pixel level PWM signal processing

Embedded DRAM for a reconfigurable array

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus

A multiple vendor 2.5-V DLL for 1.6-GB/s RDRAMs

A high-resolution capacitive fingerprint sensing scheme with charge-transfer technique and automatic contrast emphasis

CMOS fingerprint sensor with automatic local contrast adjustment and pixel-parallel encoding logic

Future perspective and scaling down roadmap for RF CMOS

Compact distributed RLC models for multilevel interconnect networks

Micro IDDQ test using Lorentz force MOSFETs

Monte Carlo modeling of threshold variation due to dopant fluctuations

1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)

Symposium 1997 on VLSI Circuits

1996 Symposium on VLSI Circuits. Digest of Technical Papers

Digest of Technical Papers., Symposium on VLSI Circuits.

Proceedings of 1994 IEEE Symposium on VLSI Circuits

Symposium 1993 on VLSI Circuits

1992 Symposium on VLSI Circuits Digest of Technical Papers

1991 Symposium on VLSI Circuits

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

Symposium 1989 on VLSI Circuits

Symposium 1988 on VLSI Circuits

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