NDLI: Latchup in CMOS

Content Provider	IEEE Xplore Digital Library
Author	Morris, W.
Copyright Year	2003
Description	Author affiliation: Silicon Eng., Austin, TX, USA (Morris, W.)
Abstract	Latchup is a failure mode in CMOS circuits that results in either soft failures with a loss of data or logic state, or in extreme cases, a destructive hard failure and permanent loss of the circuit. As isolation widths shrink, device structures become ever more susceptible to both failure modes, unless steps are taken to improve latchup robustness. The rapid proliferation of multiple power supply voltages and system-on-chip designs also exacerbate the problem. Prevention of both transient and destructive failures is of utmost importance in advanced CMOS designs. CMOS technologies have largely converged on p-bulk substrates. Reducing the CMOS power supply voltage is a potential solution for hard latchup failures, but not soft ones. This paper presents characterizations of latchup obtained by process and device modeling. Introducing a low resistance shunt layer by ion implantation is shown to be the most effective method for preventing all types of latchup failures.
Sponsorship	IEEE Electron Devices Soc. IEEE Reliability Soc
Starting Page	76
Ending Page	84
File Size	637859
Page Count	9
File Format	PDF
ISBN	0780376498
DOI	10.1109/RELPHY.2003.1197724
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-03-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Semiconductor device modeling CMOS logic circuits Power supplies MOSFET circuits Substrates Power system transients Silicon Voltage Manufacturing
Content Type	Text
Resource Type	Article

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