NDLI: Thermal breakdown of VLSI by ESD pulses

Content Provider	IEEE Xplore Digital Library
Author	Lin, D.L.
Copyright Year	1990
Description	Author affiliation: AT&T Bell Lab., Murray Hill, NJ, USA (Lin, D.L.)
Abstract	A three-dimensional thermal model to determine the temperature rise and voltage build-up of VLSI devices stressed by human-body model (HBM) electrostatic discharges (ESD) is discussed. Application of the model to a specific device is yields failure thresholds and failure sites in agreement with the experimental results. This detailed model can be used to evaluate and improve designs of ESD protection circuits. It not only reconfirms the good design principles for ESD protection circuits, but also points out the importance of pulse risetime in determining the failure site. Allowing a wide range in risetime in ESD simulator specifications (such as the 0-10 ns range in MIL-STD Method 3015.6 Notice 7 and the 2-10 ns range in the EOS/ESD Association HBM Standard), may cause ESD pulses of different risetimes within the allowable range to deposit energy to different spots in a device and yield uncorrelatable ESD thresholds.
Starting Page	281
Ending Page	287
File Size	488273
Page Count	7
File Format	PDF
DOI	10.1109/RELPHY.1990.66101
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-03-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electric breakdown Very large scale integration Electrostatic discharge Protection Thermal stresses Temperature Voltage Pulse circuits Circuit simulation Earth Observing System
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

Characterization of VLSI circuit interconnect heating and failure under ESD conditions

VLSI circuits degradation due to ESD stress below ESD rating voltage

ESD protection design using a mixed-mode simulation for advanced devices

Optimized ESD protection circuits for high-speed MOS/VLSI

High-current failure model for VLSI interconnects under short-pulse stress conditions

Whole-chip ESD protection design for submicron CMOS VLSI

Characterizing the stress applied to ICs by different ESD tester circuits

3D electro-thermal modeling of ggNMOS ESD protection structure

Thermal breakdown of VLSI by ESD pulses

Similar Documents

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

Characterization of VLSI circuit interconnect heating and failure under ESD conditions

VLSI circuits degradation due to ESD stress below ESD rating voltage

ESD protection design using a mixed-mode simulation for advanced devices

Optimized ESD protection circuits for high-speed MOS/VLSI

High-current failure model for VLSI interconnects under short-pulse stress conditions

Whole-chip ESD protection design for submicron CMOS VLSI

Characterizing the stress applied to ICs by different ESD tester circuits

3D electro-thermal modeling of ggNMOS ESD protection structure

Thermal breakdown of VLSI by ESD pulses