NDLI: A 90-nm radiation hardened clock spine

Content Provider	IEEE Xplore Digital Library
Author	Chellappa, S. Clark, L.T. Holbert, K.E.
Copyright Year	2011
Description	Author affiliation: School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, 85287-5706 USA (Chellappa, S.; Clark, L.T.; Holbert, K.E.)
Abstract	A RHBD clock distribution network is described that reliably synchronizes the flow of signals through an integrated circuit in the presence of SETs. The clock spine design controls both redundant and non-redundant hardened circuits. The design uses techniques to reduce the jitter due to SETs, as well as error detection at every clock edge, since errors may be in the clock gating enables rather than the clocks themselves. The clock spine has been fabricated and tested on both standard and a low power 90-nm test chips, and proven hard as demonstrated by both heavy ion and proton broad beam testing.
Starting Page	479
Ending Page	484
File Size	796463
Page Count	6
File Format	PDF
ISBN	9781457705854
ISSN	03796566
e-ISBN	9781457705861
DOI	10.1109/RADECS.2011.6131355
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-19
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Capacitance Synchronization Phase locked loops Jitter Logic gates Radiation hardening single event transients Radiation hardening by design clock generation single event upset
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 90-nm Radiation Hardened Clock Spine

A 90 nm bulk CMOS radiation hardened by design cache memory

A Robust Single Event Upset Hardened Clock Distribution Network

A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS

A RadHard-by-Design Clock Generator

SEU hardened clock regeneration circuits

Radiation-induced clock jitter and race

A Probabilistic Analysis Technique Applied to a Radiation-Hardened-by-Design Voltage-Controlled Oscillator for Mixed-Signal Phase-Locked Loops

Clock and Reset Transients in a 90 nm RHBD Single-Core Tilera Processor

A 90-nm radiation hardened clock spine

Similar Documents

A 90-nm Radiation Hardened Clock Spine

A 90 nm bulk CMOS radiation hardened by design cache memory

A Robust Single Event Upset Hardened Clock Distribution Network

A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS

A RadHard-by-Design Clock Generator

SEU hardened clock regeneration circuits

Radiation-induced clock jitter and race

A Probabilistic Analysis Technique Applied to a Radiation-Hardened-by-Design Voltage-Controlled Oscillator for Mixed-Signal Phase-Locked Loops

Clock and Reset Transients in a 90 nm RHBD Single-Core Tilera Processor

A 90-nm radiation hardened clock spine