NDLI: Analytical analysis of the MCUs sensitiveness of TMR architectures in SRAM-based FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Sterpone, L. Violante, M.
Copyright Year	2007
Description	Author affiliation: Politec. di Torino, Torino, Italy (Sterpone, L.; Violante, M.)
Abstract	In this paper we present an analytical analysis of the fault masking capabilities of triple modular redundancy (TMR) hardening technique in the presence of multiple cell upsets (MCUs) in the configuration memory of SRAM-based FPGAs. The analytical method we developed allow an accurate study of the MCUs sensitiveness characterizing the orientation and the effects provoking multiple domain crossing errors that defeats the TMR fault tolerance capability. From our analysis we have found that most of the failure affects configurable logic block's routing resources. The experimental analysis have been performed on two realistic case study circuits. Experimental results are presented and discussed in terms of faults effects showing in particular that 2-bits MCUs may corrupt TMR 2.6 order of magnitude more than single cell upsets (SCUs).
Starting Page	1
Ending Page	6
File Size	2176319
Page Count	6
File Format	PDF
ISBN	9781424417049
ISSN	03796566
DOI	10.1109/RADECS.2007.5205501
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-10
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Random access memory Radiation hardening Ionizing radiation Redundancy Circuit faults Logic Routing Costs Integrated circuit technology TMR Field Programmable Gate Array (FPGA) analytical analysis multiple bit upset
Content Type	Text
Resource Type	Article

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