NDLI: Design of a CMOS readout circuit for wide-temperature range capacitive MEMS sensors

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Table of contents

A reverse write assist circuit for SRAM dynamic write V tracking using canary SRAMs

Exploiting static and dynamic locality of timing errors in robust L1 cache design

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement

40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

Modeling, design and verification platform using SystemC AMS

On application of one-class SVM to reverse engineering-based hardware Trojan detection

Employing a Timed Colored Petri Net to accomplish an accurate model for Network-on-Chip performance evaluation

Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesis

Modeling and analysis of system stability in a distributed power delivery network with embedded digital linear regulators

An application-aware heterogeneous prioritization framework for NoC based chip multiprocessors

Adding virtualization support in MIPS 4Kc-based MPSoCs

HELIX: Design and synthesis of hybrid nanophotonic application-specific network-on-chip architectures

An analytical approach to system-level variation analysis and optimization for multi-core processor

Heterogeneity exploration for peak temperature reduction on multi-core platforms

Efficient post-silicon validation via segmentation of process variation envelope — Global vs local variations

Protection of Muller-Pipelines from transient faults

Runtime fault recovery protocol for NoC-based MPSoCs

Concurrency-oriented SoC re-certification by reusing block-level test vectors

Efficient trace signal selection using augmentation and ILP techniques

Directed test generation for hybrid systems

Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache

Efficient region-aware P/G TSV planning for 3D ICs

3D-ICs with self-healing capability for thermal effects in RF circuits

Comparative analysis of clock distribution networks for TSV-based 3D IC designs

Delay and power optimization with TSV-aware 3D floorplanning

Runtime 3-D stacked cache data management for energy minimization of 3-D chip-multiprocessors

Statistical methodology for modeling non-IID memory fails events

Automated Shmoo data analysis: A machine learning approach

Double patterning-aware detailed routing with mask usage balancing

Design of radiation hardened wide tuning range CMOS oscillators

Computer simulation of radiation-induced clock-perturbation in phase-locked loop with analog behavioral model

Measuring SET pulsewidths in logic gates using digital infrastructure

Fast, accurate variation-aware path timing computation for sub-threshold circuits

An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimes

Sub-threshold custom standard cell library validation

Power- and area-efficient Approximate Wallace Tree Multiplier for error-resilient systems

Predictive synchronization for DVFS-enabled multi-processor systems

Ring-based sharing fabric for efficient pipelining of kernel-stream on CGRA-based multi-core architecture

Multi-core partitioned scheduling for fixed-priority periodic real-time tasks with enhanced RBound

Minimizing clock domain crossing in Network on Chip interconnect

Optimal reliability-constrained overdrive frequency selection in multicore systems

RTL datapath optimization using system-level transformations

Dual-sided doped memristor and it's SPICE modelling for improved electrical properties

Linearly separable pattern classification using memristive crossbar circuits

Low-power programmable-logic cell arrays using nonvolatile complementary atom switch

Volume accumulated double gate junctionless MOSFETs for low power logic technology applications

Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regime

A parallel clustering algorithm for placement

An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design

Kriging bootstrapped neural network training for fast and accurate process variation analysis

Impedance modeling of the intracortical microelectrode for a reliable design of a brain activity recording system

Direct finite-element-based solver for 3D-IC thermal analysis via H-matrix representation

Compiler-directed leakage energy reduction for instruction scratch-pad memories

A framework for MPSoC generation and distributed applications evaluation

Architecture for monitoring SET propagation in 16-bit Sklansky adder

Towards more reliable embedded systems through a mechanism for monitoring driver devices communication

Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits

Application of six-sigma DMAIC methodology in the evaluation of test effectiveness: A case study for EDA tools

Systematic analyses for latching probability of single-event transients

Assessment of reliability impact on GHz processors with moderate overdrive

Study of IC aging on ring oscillator physical unclonable functions

Circuit-level approach to improve the temperature reliability of Bi-stable PUFs

Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology

Fine grained wearout sensing using metastability resolution time

Methodology to optimize critical node separation in hardened flip-flops

Asymmetric aging of clock networks in power efficient designs

Post-silicon tunable clock buffer allocation based on fast chip yield computation

Timing margin recovery with flexible flip-flop timing model

NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation

Constructing small-signal equivalent impedances using ellipsoidal norms

Sense Amplifier Pass Transistor Logic for energy efficient and DPA-resistant AES circuit

Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS

TASSER: A temperature-aware statistical soft-error-rate analysis framework for combinational circuits

PETS: Power and energy estimation tool at system-level

Impact of FinFET technology for power gating in nano-scale design

Avoiding unnecessary write operations in STT-MRAM for low power implementation

A workload-aware-design of 3D-NAND flash memory for enterprise SSDs

Statistical process variation analysis of a graphene FET based LC-VCO for WLAN applications

An efficient semi-analytical current source model for FinFET devices in near/sub-threshold regime considering multiple input switching and stack effect

Assertion-based verification for system-level designs

Coverage of compositional property sets under reactive constraints

Automated methods for eliminating X bugs

Specification and formal verification of power gating in processors

Formal verification of safety of polymorphic heterogeneous multi-core architectures

Simulation and satisfiability guided counter-example triage for RTL design debugging

FastSpot: Host-compiled thermal estimation for early design space exploration

Maximizing throughput of power/thermal-constrained processors by balancing power consumption of cores

Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding

Thermal hotspot reduction in mm-Wave wireless NoC architectures

Energy-aware scratch-pad memory partitioning for embedded systems

Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors

ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes

An energy-efficient mobile PAM memory interface for future 3D stacked mobile DRAMs

Rapid prototype and implementation of a high-throughput and flexible FFT ASIP based on LISA 2.0

Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design

Statistical analysis of process variation induced SRAM electromigration degradation

Estimating true worst currents for power grid electromigration analysis

An enlarged-partition based preconditioned iterative solver for parallel power grid simulation

A 3-D Fast Transform-based preconditioner for large-scale power grid analysis on massively parallel architectures

On pattern generation for maximizing IR drop

Design of a CMOS readout circuit for wide-temperature range capacitive MEMS sensors

Topology optimization of a passive thermal actuator

Thermal flow sensors based on printed circuit board technology

Realization of efficient RF energy harvesting circuits employing different matching technique

An integrated precision clock generator for implanted electronics with superior long-term stability

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Design of a CMOS readout circuit for wide-temperature range capacitive MEMS sensors

Content Provider	IEEE Xplore Digital Library
Author	Yucai Wang Chodavarapu, V.P.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, QC, Canada (Yucai Wang; Chodavarapu, V.P.)
Abstract	We present a capacitance readout interface circuit in bulk CMOS process which is functional at wide temperature range between $-55^{o}C$ to $175^{o}C.$ The proposed circuit uses a sigma-delta technique to convert capacitance ratio into a digital output and is suitable to provide a high-accuracy digitized output for capacitive MEMS sensors. The circuit is implemented using IBM 0.13μm CMOS technology. Simulation results show that the circuit has excellent stability over wide temperature range, as high as 0.1% accuracy between $-55^{o}C$ to $175^{o}C.$
Starting Page	738
Ending Page	742
File Size	454120
Page Count	5
File Format	PDF
e-ISBN	9781479939466
DOI	10.1109/ISQED.2014.6783400
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Temperature sensors Capacitance CMOS integrated circuits Capacitive sensors Temperature distribution CMOS technology Capacitance sensor Wide-temperature operation Bulk CMOS fabrication
Content Type	Text
Resource Type	Article

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