NDLI: High Resolution Read-Out Circuit for DNA Label-Free Detection System

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Fifteenth International Symposium on Quality Electronic Design

International Symposium on Quality Electronic Design (ISQED)

Thirteenth International Symposium on Quality Electronic Design (ISQED)

2011 12th International Symposium on Quality Electronic Design

2010 11th International Symposium on Quality Electronic Design (ISQED)

2009 10th International Symposium on Quality Electronic Design

9th International Symposium on Quality Electronic Design (isqed 2008)

Table of contents

Organizing Committee / Best Paper

Technical Subcommittee Lists

Steering/Advisory Committee

Conference at a glance

Tutorial 1: The Promise of High-k/Metal Gates-From Electronic Transport Phenomena to Emerging Device/Circuit Applications

Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies

Tutorial 3: Process Technology Development and New Design Opportunities in 3D Integration Technology

Tutorial 4: Robust System Design in Scaled CMOS

Tutorial 5: Caches in the Many-Core Era: What Purpose Might eDRAM Serve?

Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM)

Plenary Speech 1P1: Shrinking time-to-market through global value chain integration

Plenary Speech 1P2: Bounding the Endless Verification Loop

A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS

Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation

Error Protected Data Bus Inversion Using Standard DRAM Components

Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering

Fast and Accurate Waveform Analysis with Current Source Models

An Efficient Method for Fast Delay and SI Calculation Using Current Source Models

Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model

Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes

Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths

IR Drop Reduction via a Flip-Flop Resynthesis Technique

Noise Interaction Between Power Distribution Grids and Substrate

Luncheon Keynote Speech

Fundamental Data Retention Limits in SRAM Standby Experimental Results

Quality of a Bit (QoB): A New Concept in Dependable SRAM

Cache Design for Low Power and High Yield

Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations

High Output Resistance and Wide Swing Voltage Charge Pump Circuit

Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses

A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design

Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation

Dependence of Minimum Operating Voltage $(V_{DDmin})$ on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM

Accurate Temperature Estimation for Efficient Thermal Management

Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic

Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis

A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors

Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations

Variation Aware Spline Center and Range Modeling for Analog Circuit Performance

High-Quality Circuit Synthesis for Modern Technologies

ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis

Improving the Efficiency of Power Management Techniques by Using Bayesian Classification

An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems

Constant Rate Dataflow Model with Intermediate Ports for Efficient Code Synthesis with Top-Down Design and Dynamic Behavior

Thermal-Aware IR Drop Analysis in Large Power Grid

A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations

Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model

Characterization of Standard Cells for Intra-Cell Mismatch Variations

Full-Chip Leakage Verification for Manufacturing Considering Process Variations

Processor Verification with hwBugHunt

Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions

Efficient Selection of Observation Points for Functional Tests

A Novel Test Generation Methodology for Adaptive Diagnosis

Timing-Aware Multiple-Delay-Fault Diagnosis

A Dual Oxide CMOS Universal Voltage Converter for Power Management in $Multi-V_{DD}$ SoCs

Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates

A Statistic-Based Approach to Testability Analysis

Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes

On the Feasibility of Obtaining a Globally Optimal Floorplanning for an L-shaped Layout Problem

Architecting for Physical Verification Performance and Scaling

Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm

CMOS Based Low Cost Temperature Sensor

An SSO Based Methodology for EM Emission Estimation from SoCs

Fast Timing Update under the Effect of IR Drop

Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations

Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations

A Low Energy Two-Step Successive Approximation Algorithm for ADC Design

Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration

Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies

Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design

Evaluation of the PTSI Crosstalk Noise Analysis Tool and Development of an Automated Spice Correlation Suite to Enable Accuracy Validation

Hotspot Based Yield Prediction with Consideration of Correlations

A Randomized Greedy Algorithm for the Pattern Fill Problem for DFM Applications

A Passive 915 MHz UHF RFID Tag

Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner

DFM Based Detailed Routing Algorithm for ECP and CMP

Instruction Scheduling for Variation-Originated Variable Latencies

Hotspot Prevention Using CMP Model in Design Implementation Flow

The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era

Computation of Waveform Sensitivity Using Geometric Transforms for SSTA

On Efficient and Robust Constraint Generation for Practical Layout Legalization

Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family

Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures

Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs

Analytical Noise-Rejection Model Based on Short Channel MOSFET

A High-Performance Bus Architecture for Strongly Coupled Interconnects

A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS

A Holistic Approach to SoC Verification

A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips

Hybrid Integration of Bandgap Reference Circuits Using Silicon ICs and Germanium Devices

Verification of IP-Core Based SoC's

Innovative Test Solutions for Pin-Limited Microcontrollers

XStatic: A Simulation Based ESD Verification and Debug Environment

Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping

Cell Swapping Based Migration Methodology for Analog and Custom Layouts

A Knowledge-Based Tool for Generating and Verifying Hardware-Ready Embedded Memory Models

System Verilog for Quality of Results (QoR)

Power Delivery System: Sufficiency, Efficiency, and Stability

Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability

Clock Skew Analysis via Vector Fitting in Frequency Domain

An Approach for a Comprehensive QA Methodology for the PDKs

Strategies for Quality CAD PDKs

Variability Analysis for sub-100nm PD/SOI Sense-Amplifier

Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework

Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics

A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design

Adaptive Branch and Bound Using SAT to Estimate False Crosstalk

Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing

Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution

A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs

Study on the Si-Ge Nanowire MOSFETs with the Core-Shell Structure

Elastic Timing Scheme for Energy-Efficient and Robust Performance

Statistical Models and Frequency-Dependent Corner Models for Passive Devices

A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors

Analytical Model for the Propagation Delay of Through Silicon Vias

Sampling Error Estimation in High-Speed Sampling Systems Introduced by the Presence of Phase Noise in the Sampling Clock

A QoS Scheduler for Real-Time Embedded Systems

FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver

A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks

Plenary Speech 2P1: Consumerization of Electronics and Nanometer Technologies: Implications for Manufacturing Test

Plenary Speech 2P2: Statistical Techniques to Achieve Robustness and Quality

Plenary Speech 2P3: The Greening of The SoC - How Electrical Engineers Will Save The World

System-in-Package Technology: Opportunities and Challenges

Printed Circuit Board Assembly Test Process and Design for Testability

Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages

An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign

Techniques for Early Package Closure in System-in-Packages

Fast Shape Optimization of Metallization Patterns for DMOS Based Driver

MAISE: An Interconnect Simulation Engine for Timing and Noise Analysis

Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding

Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures

2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions

Automated Standard Cell Library Analysis for Improved Defect Modeling

A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test

Finite-Point Gate Model for Fast Timing and Power Analysis

Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach

Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces

Practical Clock Tree Robustness Signoff Metrics

Hierarchical Soft Error Estimation Tool (HSEET)

Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)

Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube Interconnect

Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar

Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield

High Resolution Read-Out Circuit for DNA Label-Free Detection System

Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation

Characterizing Intra-Die Spatial Correlation Using Spectral Density Method

Investigating the Impact of Fill Metal on Crosstalk-Induced Delay and Noise

Process-Variation Statistical Modeling for VLSI Timing Analysis

A Design Model for Random Process Variability

A Scratch-Pad Memory Aware Dynamic Loop Scheduling Algorithm

Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform

Runtime Validation of Transactional Memory Systems

SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems

Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect

An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node

Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation

Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems

A Basis for Formal Robustness Checking

Quantified Impacts of Guardband Reduction on Design Process Outcomes

Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits

A Root-Finding Method for Assessing SRAM Stability

Cellwise OPC Based on Reduced Standard Cell Library

On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits

Interval Based X-Masking for Scan Compression Architectures

Two New Methods for Accurate Test Set Relaxation via Test Set Replacement

Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing

A Built-in Test and Characterization Method for Circuit Marginality Related Failures

On Chip Jitter Measurement through a High Accuracy TDC

Robust Analog Design for Automotive Applications by Design Centering with Safe Operating Areas

Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation

Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect

Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method

IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization

ISQED 2009 Call for Papers

8th International Symposium on Quality Electronic Design (ISQED'07)

7th International Symposium on Quality Electronic Design (ISQED'06)

Sixth international symposium on quality electronic design (isqed'05)

International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720)

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.

Proceedings International Symposium on Quality Electronic Design

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)

High Resolution Read-Out Circuit for DNA Label-Free Detection System

Content Provider	IEEE Xplore Digital Library
Author	De Venuto, D. Ricco, B.
Copyright Year	2008
Description	Author affiliation: DEE Politecnico di Bari, Bari (De Venuto, D.)
Abstract	This paper presents novel read-out electronic systems for a fast DNA label-less detection. The capacitive shift due to the hybridization effect is monitored by means of a charge sensitive amplifier and a differential stage. The systems provide an A/D conversion and an evaluation of the capacitive shift amount with a resolution of 11 bit. The read-out solutions demonstrate the ability to identify a 0.01% variation on the capacitive value of the sensor. The investigated techniques are suitable for monolithic systems or for a micro-fabricated array of sensors.
Starting Page	708
Ending Page	711
File Size	332088
Page Count	4
File Format	PDF
ISBN	9780769531175
DOI	10.1109/ISQED.2008.4479824
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-03-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuits DNA Biosensors Capacitance Capacitive sensors Sensor systems Electrodes Gold Sensor arrays Monitoring differential read-out system. DNA biosensor read-out. Charge sensitive front-end
Content Type	Text
Resource Type	Article

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