NDLI: Shifting perspectives on DFM

Please wait, while we are loading the content...

Fifteenth International Symposium on Quality Electronic Design

International Symposium on Quality Electronic Design (ISQED)

Thirteenth International Symposium on Quality Electronic Design (ISQED)

2011 12th International Symposium on Quality Electronic Design

2010 11th International Symposium on Quality Electronic Design (ISQED)

2009 10th International Symposium on Quality Electronic Design

9th International Symposium on Quality Electronic Design (isqed 2008)

8th International Symposium on Quality Electronic Design (ISQED'07)

7th International Symposium on Quality Electronic Design (ISQED'06)

Sixth international symposium on quality electronic design (isqed'05)

Proceedings. 6th international symposium on quality electronic design

Table of contents

Technical Subcommittees

Steering/Advisory Committee

Conference at a Glance

Design of sub-90 nm circuits and design methodologies

Modeling and design of chip-package interface

IP Creation and Use What Roadblocks are Ahead or it is Just Clear and Bumpy Road?

Enabling true design for manufacturability

Recent progress and remaining challenges in pattern transfer technologies for advanced chip designs

Shifting perspectives on DFM

Toward quality EDA tools and tool flows through high-performance computing

Noise library characterization for large capacity static noise analysis tools

Two-dimensional layout migration by soft constraint satisfaction

Domain strategy and coverage metric for validation

Power supply noise-aware scheduling and allocation for DSP synthesis

Reducing power consumption during TLB lookups in a PowerPC/spl trade/ embedded processor

TFT-LCD application specific low power SRAM using charge-recycling technique

Error analysis for the support of robust voltage scaling

Analytical study of impact ionization and subthreshold current in submicron n-MOSFET

Analysis and optimization of static power considering transition dependency of leakage current in VLSI circuits

Controlled-load limited switch dynamic logic circuit

Dynamically pulsed MTCMOS with bus encoding for total power and crosstalk minimization

Charge-based core and the model architecture of BSIM5

Integration of design for manufacturability (DFM) practices in design flows

How circuit analysis and yield optimization can be used to detect circuit limitations before silicon results

Leakage current modeling in PD SOI circuits

A balanced scorecard for systemic quality in electronic design automation: an implementation method for an EDA company

Issues and challenges in ramp to production

A technique for designing totally self-checking domino logic circuits

Early assessment of leakage power for system level design

Technology mapping for reliability enhancement in logic synthesis

Evaluation of capacitor ratios in automated accurate common-centroid capacitor arrays

Closing the gap between carry select adder and ripple carry adder: a new class of low-power high-performance adders

Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture

Testing for resistive shorts in FPGA interconnects

TED thermo electrical designer: a new physical design verification tool

A fast lithography verification framework for litho-friendly layout design

Gate-level mitigation techniques for neutron-induced soft error rate

Exact algorithms for coupling capacitance minimization by adding one metal layer

Design of a 10 bit TSMC 0.25 /spl mu/m CMOS digital to analog converter

A high-performance SRAM technology with reduced chip-level routing congestion for SoC

Design and evaluation of a security scheme for sensor networks

A minimum cut based re-synthesis approach

Analysis for complex power distribution networks considering densely populated vias

Buffer planning algorithm based on partial clustered floorplanning

IP quality: a design, not a verification problem

Reseeding-based test set embedding with reduced test sequences

Reduced test application time based on reachability analysis

Using MUXs network to hide bunches of scan chains

BIST-guided ATPG

Dynamic test compaction for bridging faults

A min-variance iterative method for fast smart dummy feature density assignment in chemical-mechanical polishing

Standard cell printability grading and hot spot detection

Performance-driven OPC for mask cost reduction

Meeting nanometer DPM requirements through DFT

Parametric yield analysis and constrained-based supply voltage optimization

Power-delay metrics revisited for 90 nm CMOS technology

Optimization of individual well adaptive body biasing (IWABB) using a multiple objective evolutionary algorithm

Electromigration reliability comparison of Cu and Al interconnects

Combining system level modeling with assertion based verification

Low voltage test in place of fast clock in DDSI delay test

Functional verification of networked embedded systems

Functions for quality transition fault tests

Noise aware decoupling capacitors for multi-voltage power distribution systems

P/G pad placement optimization: problem formulation for best IR drop

Impact of on-chip inductance on power distribution network design for nanometer scale integrated circuits

Power grid planning for microprocessors and SoCs

A power-aware GALS architecture for real-time algorithm-specific tasks

An ILP formulation for reliability-oriented high-level synthesis

Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations

Reliability-centric hardware/software co-design

Deep submicron CMOS integrated circuit reliability simulation with SPICE

Modeling layout effects for sensitivity-based analog circuit optimization

In-circuit self-tuning of clock latencies

Statistical analysis of clock skew variation in H-tree structure

Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits

Design for degradation: CAD tools for managing transistor degradation mechanisms

A practical transistor-level dual threshold voltage assignment methodology

Analysis and design of LVTSCR-based EOS/ESD protection circuits for burn-in environment

Built-in-self-testing techniques for programmable capacitor arrays

A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC

A built-in self-test scheme for differential ring oscillators

Power reduction in test-per-scan BIST with supply gating and efficient scan partitioning

Nanoelectronics: Evolution or Revolution?

Plenary Session 2P

Quality and EDA

IP quality: a new model that faces methodology and management challenges

SoC engineering trends as impacted by new applications and system level requirements

ASLIC: a low power CMOS analog circuit design automation

Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models

A mask reuse methodology for reducing system-on-a-chip cost

Design of high performance sense amplifier using independent gate control in sub-50nm double-gate MOSFET

Simulating and improving microelectronic device reliability by scaling voltage and temperature

Predicting and designing for the impact of process variations and mismatch on the trim range and yield of bandgap references

Modeling intrinsic fluctuations in decananometer MOS devices due to gate line edge roughness (LER)

Modeling within-die spatial correlation effects for process-design co-optimization

Robust multi-level current-mode on-chip interconnect signaling in the presence of process variations

A comprehensive methodology for noise characterization of ASIC cell libraries

Sensitivity-based gate delay propagation in static timing analysis

Fast decap allocation algorithm for robust on-chip power delivery

Clock trees: differential or single ended?

Exploring the challenges in creating a high-quality mainstream design solution for system-in-package (SiP) design

Design and analysis of area-IO DRAM/logic integration with system-in-a-package (SiP)

Physical design of optoelectronic system-on-a-package: a CAD tool and algorithms

Concurrent chip package design for global clock distribution network using standing wave approach

Current calculation on VLSI signal interconnects

Dummy filling methods for reducing interconnect capacitance and number of fills

Voltage scaling, wire sizing and repeater insertion design rules for wave-pipelined VLSI global interconnect circuits

Interconnect delay and slew metrics using the first three moments

Passive hierarchical model order reduction and realization of RLCM circuits

Reticle floorplanning and wafer dicing for multiple project wafers

Obstacle-avoiding rectilinear minimum-delay Steiner tree construction towards IP-block-based SOC design

Wire planning with bounded over-the-block wires

Floorplanning with consideration of white space resource distribution for repeater planning

Thermal-aware floorplanning using genetic algorithms

Joint equalization and coding for on-chip bus communication

A more effective C/sub EFF/

An interconnect insensitive linear time-varying driver model for static timing analysis

Design of a band-pass pseudo-2-path switched capacitor ladder filter

Design considerations for low-power ultra wideband receivers

A new method for design of robust digital circuits

Staggered twisted-bundle interconnect for crosstalk and delay reduction

Analysis of wave-pipelined domino logic circuit and clocking styles subject to parametric variations

Impact of interconnect process variations on memory performance and design

Participating Organizations

Best Paper Award

ISQED 2006 Call for Papers

International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720)

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.

Proceedings International Symposium on Quality Electronic Design

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)

Shifting perspectives on DFM

Content Provider	IEEE Xplore Digital Library
Author	Sawicki, J.
Copyright Year	2005
Description	Author affiliation: Mentor Graphics Corp., Beaverton, OR, USA (Sawicki, J.)
Abstract	Summary form only given. There is one universal truth in terms of design for manufacturing (DFM) - DFM tools and disciplines have always existed. In micron technologies, DFM methodologies were applied to ensure acceptable yield and adequate test coverage. However, nanometer technology has ushered in new and significant yield and manufacturing considerations and constraints. The lack of a major increase in yield improvement between the 350 nm and 180 nm nodes suggests that yield loss mechanisms are not only increasing, but they are increasing fast enough that 'cosmetic' improvements in tools and methodologies are largely offset. If EDA tools are to assist the semiconductor industry at the 90 nm and 65 nm nodes, there must be profound changes to existing tools, and the introduction of new technologies that allow designers to consider and optimize for manufacturing at each stage of the design, verification, tapeout and test process. Where will these new tools and capabilities appear? They will show up in all parts of the design flow, and also on the manufacturing floor. In particular, an immediate focus for the EDA industry must be to deliver new technology in four key areas: process modeling (electrical and lithographic); statistical analysis and visualization; design optimization; test and inspection.
Sponsorship	IEEE Electron Device Soc. (EDS) IEEE Components, Packaging & Manuf. Technol. Soc. (CPMT)
File Size	733308
File Format	PDF
ISBN	0769523013
DOI	10.1109/ISQED.2005.109
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-03-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design for manufacture Electronic design automation and methodology Design optimization Electronics industry Manufacturing processes Semiconductor device manufacture Semiconductor device testing Manufacturing industries Statistical analysis Visualization
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in