NDLI: Application-specific architectures for field-programmable VLSI technologies

Content Provider	IEEE Xplore Digital Library
Author	Gebotys, C.H. Gebotys, R.J.
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada (Gebotys, C.H.)
Abstract	New field-programmable gate array (FPGA) technologies have increased the industrial interest in tools which map a DSP application and a set of performance constraints to a specific VLSI architecture. This paper presents an optimization methodology for mapping a DSP application and a set of performance constraints into an architecture targeted for FPGA technologies with user-programmable RAM blocks on chip. The target architecture supports multiple register files, multiple busses, complex types of functional units, and multichip implementation. The optimization methodology presented in this paper maps DSP applications to optimized register file architectures suitable for FPGAs using a number of different integer programming models. A new integer programming model is presented and used to minimize the number of busses required in the application-specific architectures. Results show that the optimization methodology provides architectures with 22% fewer bus connections than previous research in practical cpu times. For the first time this research provides industry with 1) a high level design optimization methodology that synthesizes application-specific DSP architectures for implementation in new field programmable VLSI technologies, and 2) a methodology to support fast prototyping of DSP applications using multiple FPGA chips.
Starting Page	124
Ending Page	130
File Size	641900
Page Count	7
File Format	PDF
ISBN	0818650907
DOI	10.1109/HICSS.1994.323178
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-01-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Field programmable gate arrays Digital signal processing chips Prototypes Throughput Delay Registers Optimization methods Computer architecture Psychology
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A High Performance VLSI FFT Architecture

VLSI Designer's interface

High Performance 16K, 64K, 256K complex points VLSI Systolic FFT Architectures

Family of folded bit-serial multipliers

Real-time sound localization using field-programmable gate arrays

Power and Area Efficient VLSI Architectures for Communication Signal Processing

Real-time sound localization using field-programmable gate arrays

DSP-specific field-programmable VLSI and its CAD environment

Programmable DSP systems using FPGA

Application-specific architectures for field-programmable VLSI technologies

Similar Documents

A High Performance VLSI FFT Architecture

VLSI Designer's interface

High Performance 16K, 64K, 256K complex points VLSI Systolic FFT Architectures

Family of folded bit-serial multipliers

Real-time sound localization using field-programmable gate arrays

Power and Area Efficient VLSI Architectures for Communication Signal Processing

Real-time sound localization using field-programmable gate arrays

DSP-specific field-programmable VLSI and its CAD environment

Programmable DSP systems using FPGA

Application-specific architectures for field-programmable VLSI technologies