NDLI: A Comparative Study of Three Designs for Sub Half Micron Buried p-channel MOSFET

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A Comparative Study of Three Designs for Sub Half Micron Buried p-channel MOSFET

Content Provider	IEEE Xplore Digital Library
Author	Guegan, G. Lerme, M. Deleonibus, S. Reimbold, G.
Copyright Year	1994
Description	Author affiliation: GRESSI-LETI (CEA-Technologies Avancées), DMEL-CENG 38054 Grenoble Cedex 9 France (Guegan, G.; Lerme, M.; Deleonibus, S.; Reimbold, G.)
Abstract	This paper reports a comparison between three designs of p-channel MOSFETs processed with n+ doped polysilicon gates. Two new techniques to reduce DIBL of buried channel pMOSFETs are proposed and compared with a conventional approach. Criteria for this comparison are the short channel effect control, the off-state leakage current, the holding voltage and the saturation drain current. Based on extensive simulations and experimental work, a 0.30 ¿m physical gate length device with weak DIBL and high drivability is achieved.
Starting Page	325
Ending Page	328
File Size	359349
Page Count	4
File Format	PDF
ISBN	0863321579
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-09-11
Publisher Place	Scotland
Access Restriction	Subscribed
Rights Holder	Editions Frontieres
Subject Keyword	MOSFET circuits Implants Leakage current Boron Threshold voltage Doping Voltage control Process design Fabrication CMOS process
Content Type	Text
Resource Type	Article

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