NDLI: Breakdown triggering in PM-HEMTs studied by means of Monte Carlo simulator

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2015 45th European Solid State Device Research Conference (ESSDERC)

2014 44th European Solid State Device Research Conference (ESSDERC)

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

2010 Proceedings of the European Solid State Device Research Conference

2009 Proceedings of the European Solid State Device Research Conference

ESSDERC 2008 - 38th European Solid-State Device Research Conference

ESSDERC 2007 - 37th European Solid State Device Research Conference

2006 European Solid-State Device Research Conference

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.

32nd European Solid-State Device Research Conference

31st European Solid-State Device Research Conference

30th European Solid-State Device Research Conference

29th European Solid-State Device Research Conference

Volume 1 - 1999

ESSDERC 1999 Title Page

Conference organization

ESSDERC 1999 Table of contents

The first Product on 300 mm Wafer - 64 Mb DRAM

Mainstreaming of SOI Technology

Interconnect Design Strategy for High-Speed Logic LSIs

New Electronic Device Opportunities Afforded by GaN-based materials

Silicon Single Electron and Small Electron Number Transistors and Circuits

CMOS Integrated Chemical Microsensors and the Electronic Nose

Impact of plasma-charging damage to the scaling limit of thin gate-oxide

Probing Semiconductor Devices on the Nanometer Scale

Status and Trends in Silicon RF Technology

Advanced Flip Chip Technologies

Reliability of Ultra-thin Oxides for the Giga-bit generations

SOI Devices and Technology

75 GHz Bipolar Production Technology for the 21st Century

Challenges in Compact Modelling of Future RF CMOS

Modeling and Optimisation of Optoelectronic devices

Trends and Issues in BCD Smart Power Technologies

The decananometer CMOS era - Is there CMOS after CMOS?

Embedded Non Volatile Memories In Deep-Submicron CMOS

Dopants, Defects, Clusters: A Process Modelling Taxonomy

Device Characteristics of Metal Gate MOSFETs utilizing Denudation of WNx on Polycrystalline Si

Metal Gates for 0.15 um CMOS and beyond

Investigations of Dual Ge Gate Integration in Advanced CMOS Process

Gate polysilicon optimization for deep-submicron MOSFETs

Capacitance Degradation due to Fringing Field in Deep Sub-Micron MOSFETs with High-K Gate Dielectrics

Impact of Plasma Density and Pattern Aspect Ratio on Plasma Damage in deep submicron CMOS technologies

Electrical Characterization and Modelling of Ultra-thin (1.8-3.4 nm) Gate Oxides

Non-Invasive Optical Characterisation Technique for Fast Switching CMOS Circuits

Implications of pocket optimisation on analog performance in deep sub-micron CMOS

A 0.13um CMOS Technology for Low-Voltage Analogue Applications

Impact of Random Dopant Placement on CMOS Delay and Power Dissipation

Influence of the Polysilicon Gate on the Random Dopant Induced Threshold Voltage Fluctuations in Sub 100 nm MOSFETs with Thin Gate Oxides

Nanopotentiometry: Data Interpretation and Quantification

Investigation of Stress in STI using UV-Raman Spectroscopy

Advanced Nitrogen Preimplant Gate Oxide Technique for Suppression of RNWE and RSCE for 0.18 um CMOS Technology

Impact of floating-body effect on RF performances of SOI MOSFET

Comparison between Short Channel Bulk (Silicon) and Body-Tied Partially Depleted SOI nMOS for High Frequency Low Voltage Analog Circuit Design

A 67 GHz fmax Lateral Bipolar Transistor with Co-silicided Base Electrode Structure on Thin Film SOI for RF Analog Applications

A LDMOS Technology Compatible with CMOS, BJT, and Passive Components for Integrated RF Power Amplifiers

Innovating SRAM Design for Fast Process Related Defect Recognition and Failure Analysis

A Cost Effective Integration Technology for High Density DRAM merged with High Performance Logic

Co-Silicide Junction Leakage and Device Characteristics in Embedded DRAM with Stack Capacitor Structure

Investigation of the Formation Mechanism of Hemispherical Grained Silicon (HSG-Si) on Undoped and Doped Amorphous Silicon for DRAM Applications

Impact of the Velocity Overshoot on the Performance of NMOSFETs with Gate Lengths from 80 to 250nm

A Unified Analytical Model for Bulk and Surface Mobility in Si n- and p-Channel MOSFET's

Charge-Sheet Analytical Model for Amorphous-Silicon TFTs

Full quantummechanical treatment of charge leakage in MOS capacitors with ultra-thin oxide layers

Excess Noise in Sub-micron Silicon FET: Characterization, Prediction and Control

Measurements of Mechanical Stress Drift in IC Plastic Packages using the Piezo-Hall Effect

Time Dependency of the Planarization Process in Copper Chemical-Mechanical Polishing

Analysis of Process Influence on HSQ Dielectric and Impact on CMOS Circuit Performance

Mechanical lapping, handling and transfer of ultra-thin wafers

Hybrid Integration of Spin-Valves and MESFETS: Technology Test for Future MRAM

Reliability of Magnetic Tunnel-Junctions

Evaluation of Room Temperature Wafer Bonding by Fabrication of a GaAs/Pt/Si Metal Base Transistor

1/f Noise in HgCdTe MWIR Photovoltaic Detectors Fabricated Using a Novel Junction Formation Technology

Effect of irradiation on AlGaAs/GaAs p-HEMTs

Multiple SiGe Quantum Wells - Novel Channel Architecture for 0.12 um CMOS

Low temperature analysis of 0.25 T-Gate SiGe n-MODFET

Ge p-MOSFETs Compatible with Si CMOS-Technology

Study on Enhanced Performance in NMOSFETs on Strained Silicon

Low frequency noise characterisation of submicron vertical heterojuncton pMOSFETs

Innovative Detectors for Ultra-high Sensitivity Laser Scanning Microscopy

Full Characterization and Long-Term Stability of Standard CMOS Materials for Integrated Micromechanical Applications

High rate CVD-diamond etching for high temperature pressure sensor applications

Novel Surface-Micromachined Thermal Actuator for Fracture and Reliability Characterisation of Polysilicon by Electrical Wafer-Level Testing

Low Pressure Detection by Depletion Channel MOS Transistors

Integrated High-speed, High-responsivity Photodiodes in CMOS and BiCMOS Technology

In-Situ Arsenic Doped Single-Crystal Emitters for Low 1/f Noise Self-Aligned SiGe HBTs

Effects of Carbon Doping on the 1/f noise in SiGe HBTs

Leakage Current Mechanisms Associated with Selective Epitaxy in SiGe Heterojunction Bipolar Transistors

Characteristics of Deep Traps in Si(1-x)Ge(x) Epitaxial Base Submicron Bipolar Transistors

Reliability of Ultra-thin MOS Gate Oxides under Constant Voltage Stressing: Do They Break Down?

The effect of elevated temperature on the reliability of very thin oxide films

Reliability Issues of Through-the-Gate-Implanted Utra-Thin Gate Oxides

Low Temperature Generation of Stress Induced Leakage Current. Degradation Mechanism: E or 1/E Model?

Time stability of Stress Induced Leakage Current in thin gate oxides

Investigation of the Threshold Voltage Difference between Partially-Depleted SOI and bulk CMOS transistors

Versatile RF Measurement System to Thoroughly Evaluate the Non-linear Behaviour of SOI versus Bulk CMOS Technologies

Detailed Analysis of Short-Channel SOI DT-MOSFET

Suitability of Elevated Source/Drain for Deep Submicron CMOS

High performance raised Gate/Source/Drain transistors for sub-0.15 um CMOS technologies

Ultra-Shallow extensions for industrial 0.15 um CMOS technology fabricated using Plasma Doping

Epi Channel MOSFETs With Low Junction Capacitances

Performance, New Short and Narrow Channel Effects and Manufacturability with Si Epitaxial channel for low voltage and low power 0.12/0.18 um CMOS applications

On the difference in threshold voltage dependence on channel length for boron and indium channel nMOS transistors

Channel Engineering for the Reduction of Random-Dopant Placement-Induced Threshold Voltage Fluctuations in Vertical sub-100nm MOSFETs

Gate Stack Optimisation for Advanced CMOS Process

Electrical Characteristics of Ultra-thin Gate Oxide Prepared by Oxidation in D2O

Silicon Nitridation by Nitric Oxide (NO) for Ta2O5 Gate Dielectric Application in MOS Devices

The Effect of Oxide Patterned Layers on the Rapid Thermal Oxidation of Polycrystalline Silicon

The Effect of Thin Oxide Layers on Shallow Junction Formation

Structure and Memory Effects of Low Energy Ge-Implanted Thin SiO2 Films

A 0.35um BiCMOS Process with Selective Epitaxial SiGe Bipolar Transistors

Narrow Decaborane (B10H14) Implanted Base For High-Speed Si Bipolar Transistors

A Complementary BiCMOS Technology for Low Power Wireless Telecommunication Applications

A validation method for parasitic capacitance extraction

Novel Parameter Extraction Techniques for Low-Voltage, Low-Power Technologies

Direct Extraction of Intrinsic Excess Phase Shift Time Constants in SiGe HBTs

An Extended BSIM3v3 Model Card for a Vertical 130 nm p-MOSFET

A General Model for MOS Transistor Matching

Efficient Methodologies for Statistical Characterisation of Analogue Designs for Submicron CMOS Technologies

1/f Noise Simulation in a-Si TFTs over Linear, Saturation and Subthreshold Regions. Comparison to BSIM Model

Compact modeling of high-frequency distortion in bipolar transistors

Compact MOS/Bipolar Charge-Control Models of Partially-Depleted SOI CMOS Devices for VLSI Circuit Simulation - SOI-Technology (ST)-SPICE

A simple model for analogue applications of dynamic threshold MOSTs

Towards a Compact Model for MOSFETs with Direct Tunneling Gate Dielectrics

A robust curve tracing scheme for the simulation of bipolar breakdown characteristics with nonlocal impact ionization models

Simulation of 0.15 Micron CMOS Device Performance

Gate Workfunction Engineering for Deep Submicron CMOS

Closed-Loop CMOS Gate Delay Time Optimization

3D Numerical Simulation for Assisting External Latch-up Protection Test Structure Design

GaAs/AlGaAs Interminiband Unipolar Semiconductor Laser at 13 um

Record Efficiencies from Planar Light-Emitting Diodes

Modulation Behaviour of Highly Efficient Non-Resonant Cavity Light-Emitting Diodes

Resonant-Cavity-Enhanced Photodiode Using Silicon-on-Anything Technology

Impact of the SOI Substrate Parameters on the Radio-frequency Performance of the Quasi-SOI Power MOSFET

Silicon Stacked Transistor with Source and Drain Tunnel Barriers

0.15um Leff Buried Channel PFET Device Design

A new method for temperature determination of integrated DMOSFETs

Off-State Breakdown in GaAs Power HFETs

Breakdown triggering in PM-HEMTs studied by means of Monte Carlo simulator

High-Breakdown and High-Linearity Ga(0.51)In(0.49P)/In(0.15)Ga(0.85)As Pseudomorphic HEMT's Prepared by Selectively Removing Mesa Sidewalls

Noise modeling of InP- based base and collector self-aligned double heterojunction bipolar transistors

High-Performance Delta-Doped InGaP/GaAs Heterojunction Bipolar Transistors

Performance and Reliability of 70nm NMOSFETs with Indium Retrograde Doping Channels

High performance 0.12 um nMOSFETs with nitrogen implanted epitaxial channels

Impact of Elevated Source/Drain on the Reverse Short Channel Effect

Sub-0.1um MOSFETs with Sb source/drain extensions

Limitations to Adaptive Back Bias Approach for Standby Power Reduction in deep sub-micron CMOS

A New Lifetime Extrapolation Technique for LDD NMOSFETs under Hot-Carrier Degradation

Impact of Electrical Stress on Hot-Electron Injection in Ultra-Thin SiO2 Films

Hot-Carrier Induced Interface Degradation in Jet Vapor Deposited SiN MNSFETs as Studied by a Novel Charge Pumping Technique

Study of bipolar transistor action during ESD stress in smart power ESD protection devices using interferometric temperature mapping

A Compact MOSFET Breakdown Model for Optimization of Gate Coupled ESD Protection Circuits

Stress evolution of low frequency (RTS) noise and leakage current in grounded-gate nMOSFET ESD protection devices

Back-bias Enhanced Source-Side Injection in 0.25um Embedded Flash Memories

Trade-Off Between Programming Speed and Current Absorption in Flash EEPROM Memories

1.8 um2 High Density Flash Memory for 0.35 um Embedded Applications

Scaling low power embedded flash EEPROMs to 0.18um

High density EEPROM cell for 0.35um embedded applications

Optimisation of Critical Parameters in a Low Cost, High Performance Deep Submicron CMOS Technology

A 0.18um Dual Gate (3.5nm/6.8nm) CMOS Technology with Copper Metallurgy for Logic, SRAM, and Analog Applications

A High Performance 0.18 um Elevated Source/Drain Technology with Improved Manufacturability

Effects of Ge Preamorphization on the Specific Contact Resistance of TiSi2 to Silicon

Scalability of Ti-salicide Process for sub-0.1um Gate Lengths: Optimization of Arsenic Preamorphization Process

On the Basic Correlation between Polysilicon Resistor Linearity, Matching and 1/f Noise

MOS Model 9 based Non-Quasi-Static Small-Signal Model for RF Circuit Design

RF modelling for 0.1um gate length MOSFETs

Reliable extraction of RF figures-of-merit for MOSFETs

Large Signal Modeling and Verification of Silicon RF Power Transistors

Accurate and Fast Modelling of Planar Inductors in CMOS Technologies

Analysis of Circular Spiral Inductors on CMOS Substrates

Simulation of a Coating Protection for an In Situ Ellipsometer in a CVD Furnace

Lateral dependence of dopant-number threshold voltage fluctuations in MOSFETs

Investigation of the Suppression of the Narrow Channel Effect in Deep Sub-Micron EXTIGATE Transistors

Simulation study of the impact of channel doping profiles on MOSFET analog performances

Poly-Si/-Si(1-x)Ge(x)/Si Sandwiched Conductivity Modulated TFT for High-Voltage Drivers in Large Area Electronic Applications

New Findings on Hot-Carrier Stress in Large Grain Excimer Annealed N-Channel Polysilicon TFTs

Analysis of defects in solid phase crystallized and laser crystallized unhydrogenated polysilicon thin film transistors

Field Effect in Organic Devices Based on Solution-Doped PPV

Ultra-Thin Elevated Channel Low Temperature Poly-Si TFTs for Fully-Integrated AMLCD Systems on Glass

A Silicon Backplane Technology for Microdisplays

Base current kink effect in SiGe HBT's

Anomalous Collector-Base Leakage in Selectively Grown SiGe-Base Heterojunction Bipolar Transistors

SiGe HBT Performance Improvements from Lateral Scaling

A high speed SiGe HBT process using non-selective epitaxy and in situ phosphorus doped polysilicon emitter: Optimization of device design rules

High Tunnelling Current Density in Silicon/Silicon-Germanium Junctions

Low-Voltage Emitter-Ballasting-Resistor-Free SiGe Power Heterojunction Bipolar Transistor for Wireless Applications

28th European Solid-State Device Research Conference

27th European Solid-State Device Research Conference

ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference

ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference

ESSDERC '94: 24th European Solid State Device Research Conference

ESSDERC '93: 23rd European solid State Device Research Conference

ESSDERC '92: 22nd European Solid State Device Research conference

ESSDERC '91: 21st European Solid State Device Research Conference

ESSDERC '90: 20th European Solid State Device Research Conference

ESSDERC '89: 19th European Solid State Device Research Conference

ESSDERC '88: 18th European Solid State Device Research Conference

ESSDERC '87: 17th European Solid State Device Research Conference

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