NDLI: Successful integration of an ultra low thermal budget process solution based on solid phase epitaxy for sub-50nm CMOS technologies

Content Provider	IEEE Xplore Digital Library
Author	El Farhane, R. Pouydebasque, A. Laviron, C. Morin, P. Arnaud, F. Stolk, P. Boeuf, F. Skotnicki, T. Bensahel, D. Halimaoui, A.
Copyright Year	2004
Description	Author affiliation: Philips Semicond. Crolles, Crolles, France (El Farhane, R.; Pouydebasque, A.)
Abstract	We demonstrate in this paper the viability of an ultra-low thermal budget CMOS process enabling the formation of ultra shallow junctions with competitive transistor characteristics. In particular, it is shown that the use of self-amorphizing implants for the source/drain (S/D) leads to a good transistor performance without significantly deteriorating the diode leakage. Moreover, it is proved that specific attention must be paid to salicidation with an ultra low thermal budget. Since the highest temperature used after gate definition is 700/spl deg/C, this process is perfectly suitable for the integration of temperature sensitive modules such as high-k dielectrics, metal gates or strained channels.
Starting Page	133
Ending Page	136
File Size	232914
Page Count	4
File Format	PDF
ISBN	0780384784
DOI	10.1109/ESSDER.2004.1356507
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-23
Publisher Place	Belgium
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Solids Epitaxial growth CMOS process Annealing Implants Boron Silicon Temperature sensors High-K gate dielectrics
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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