NDLI: A Class-D CMOS DCO with an on-chip LDO

Content Provider	IEEE Xplore Digital Library
Author	Fanori, L. Mattsson, T. Andreani, P.
Copyright Year	2014
Description	Author affiliation: Ericsson Modem, Lund, Sweden (Mattsson, T.) \|\| Lund Univ., Lund, Sweden (Fanori, L.; Andreani, P.)
Abstract	This paper presents the co-design of a class-D digitally-controlled oscillator (DCO) and a low-dropout voltage regulator (LDO) generating the supply voltage for the DCO. Despite the high intrinsic supply pushing of the class-D oscillator topology, the LDO noise has only a very marginal impact on the DCO phase noise. The class-D DCO and LDO have been integrated in a 65 nm CMOS process without any thick top metal layer. The oscillation frequency is tunable between 3.0 GHz and 4.3 GHz, for a tuning range of 36%, with a fine frequency step below 3kHz and a fine frequency range of 10 MHz (both measured at 3GHz). Drawing 9.0 mA from 0.4V (corresponding to an unregulated supply voltage of 0.6 V), the phase noise is -145.5 dBc/Hz at a 10 MHz offset from a 3.0GHz carrier. The resulting FoM is 189.5 dBc/Hz, and varies less than 1dB across the tuning range. The FoM increases to above 190 dBc/Hz when the regulated supply voltage is 0.5 V.
Starting Page	335
Ending Page	338
File Size	3321684
Page Count	4
File Format	PDF
ISBN	9781479956944
ISSN	19308833
e-ISBN	9781479956968
DOI	10.1109/ESSCIRC.2014.6942090
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-22
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase noise Tuning CMOS integrated circuits Frequency measurement Voltage-controlled oscillators voltage regulator VCO DCO class-D low phase noise high efficiency CMOS low-voltage LDO
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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