NDLI: Rapid design of complex DSP cores

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Table of contents

Taking DRAM from 4 MBytes/s to 4 GBytes/s

Contactless chipcards - trends and techniques

Very high-speed digital subscriber lines (VDSL)

Digital television — A quick circuit of next grand prix for semiconductor industry

Hearing instruments go digital

Microelectronics in automotive applications - technical and economic impact

Advances in BJT techniques for high-performance transceivers

A -90 dB THD rail-to-rail input opamp using a new local charge pump in CMOS

A 3.3 volt, low distortion ISDN line driver with a novel quiescent current control circuit

A wide range dB-linear variable gain CMOS amplifier

Embedded 5V-to-3.3V voltage regulator for supplying digital ICs in 3.3V CMOS technology

A wide band tuning system for fully integrated satellite receivers

An lower ISM band frequency synthesizer and GMSK data modulator

A 3-V delay-modulated PLL synthesizer for analog FM transmitters

A 15-bit 2 MHz Nyquist rate ΔΣ ADC in a 1 µm CMOS technology

A 74dB dynamic range, 1.1-MHz signal band 4th-order 2-1-1 cascade multi-bit CMOS ΣΔ modulator for ADSL

A 16 bit 500ks/s 2.7V 5mW ADC/DAC in 0.8um CMOS using error-correcting successive approximation

Single bit sigma-delta modulator with nonlinear quantization for µ-law coding

A fully-integrated CMOS AM radio receiver for wrist-watch calibration

Low-power offset-calibrated CMOS I/Q transmit interface for portable communications

A fully-integrated FM discriminator for RDS applications

2.5Gb/s ATM physical layer controller in 0.8µm BiCMOS

A 3.3V power adaptive 1244/622/155 Mb/s transceiver for ATM, SONET/SDH

Robust CMOS compander

A 3.3 V 350 MHz 0.35 µm CMOS programmable RIF based on redundant coding in a bit plane architecture

A novel driver architecture capable of driving high capacitive loads for sub-half micron technologies

A low-power low-voltage digital bus interface for MCM-based microsystems

Implementation of a 5×5 trits multiplier in a quasi-adiabatic ternary CMOS logic

A direct conversion IC for digital satellite TV

An ISM band transceiver chip for digital spread spectrum communication

The impact of scaling down to deep-submicron on CMOS RF circuits

A low-voltage CMOS downconversion mixer for RF applications

1.25 Gb/s CMOS differential transimpedance amplifier for gigabit networks

REMBRANDT: A RF ASIC for DECT TDMA applications

An IF-strip with integrated 2nd IF filter for a triple conversion GPS receiver

A 1V CMOS fully-differential switched-opamp bandpass ΣΔ modulator

A 2.5MHz 55dB switched-current bandpass ΣΔ modulator for AM signal conversion

A 12bit medium-time analog storage device in a CMOS standard-process

Building blocks for low-power stochastic pulse coded systems

A 0.9V, 30µW feature extractor for remote speech recognition

A 0.5mW passive telemetry IC for biomedical applications

A resistance variation tolerant constant power heating circuit for integrated sensor applications

New two single-port GaAs memory cell

Novel level-identifying circuit for flash multi-level memories

Practical low power design architecture for 256 Mb DRAM

A low noise folded bit-line sensing architecture for multi-Gb DRAM with ultra high density $6F^{2}cell$

A high speed SRAM macro for 0.35µm low voltage SOI/CMOS gate arrays

A CMOS chopper opamp with integrated low-pass filter

Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

Accurate simulation of phase noise in oscillators

CMOS circuit technique for serial IC interconnection up to 1.1 Gb/s

A direct digital synthesizer with an on-chip D/A-converter

1-V low-noise 200 MHz relaxation oscillator

A wide-tunable translinear second-order oscillator

A switched current, switched capacitor temperature sensor in 0.6u CMOS

A 9-channel time-to-digital converter for an imaging lidar application

CMOS photosensor arrays with on-chip signal processing

A 5-bit 150 MS/s, 3.3 V CMOS A/D converter with a 32 step adjustable reference circuit

Realization of a 10 MHz integrated bipolar DECT band-pass filter

10-MHz 60-dB dynamic-range 4th-order butterworth lowpass filter

High-accuracy charge-redistribution switched-capacitor video bandpass filter in standard 0.8 µm CMOS

A low-voltage power and area efficient BiCMOS log-domain filter

A high-Q bandpass fully differential SC filter with enhanced testability

An EEPROM in a standard CMOS technology

Mismatch modelling for large area MOS devices

FET mobility degradation and device mismatch due to packaging induced die stress

Drain current mismatch in SOI CMOS current mirrors and D/A converters due to localised internal and coupled heating

Low-power 200Msps, area efficient, 5-tap programmable FIR filter

Rapid design of complex DSP cores

R, G, B acquisition interface with line locked clock generator, for LCD driver

Read front end of a new AC coupled preamplifier for 300 Mb/s hard disk drives using single stripe magneto resistive heads

A robust analogue interface system for sub-micron CMOS video DSP

A low-power, high-speed 0.25µm GaAs D-FF

Reduced complexity two-phase micropipeline latch controller

Novel high-speed and low-power dynamic MOS flip-flops for a low-power 1.25GHz multiplexer/demultiplexer

A high speed, low power 8-tap digital FIR filter for PRML disk-drive read channels

A novel 1.5-V CMOS operational amplifier

A generic CAD model for arbitrarily shaped and multi-layer integrated inductors on silicon substrates

A high resolution electron imaging integrated circuit

A current-mode ASIC for use with position sensitive detector arrays

A high resolution time-to-digital converter based on time-to-voltage interpolation

A 5V CMOS chip for interpolation of sine/cosine signals

A 1.2µ BiCMOS realization of a low power and offset-free voltage/frequency converter

Integrated RF transmitter based on SAW oscillator

Hierarchical N-port memory architecture based on 1-port memory cells

A 1V bootstrapped CMOS digital logic family

A full-custom self-timed DSP processor implementation

High speed arithmetic design using CPL and DPL logic

A 1 GHz, 40 mW fully integrated continuous-time second-order bandpass filter in GaAs technology

Multilevel decoder-decision circuit for high bitrate ETDM transmission

10 Gb/s single-chip data regeneration with an injection synchronised ring oscillator and an automatic phase adjustment

Constructing high level macrocell models using the Shlaer-Mellor method

A 1mW only wireless phone voiceband D to A CODEC

A variable gain transimpedance amplifier channel with a timing discriminator for a time-of-flight laser radar

A 200 MHz cell for a parallel-successive-approximation ADC in 0.8 µm CMOS, using a reference pre-select scheme

A low-voltage, high-speed and low-power full current-mode video-rate CMOS A/D converter

A 103MHz open-loop full CMOS highly-linear sample-and-hold amplifier

Performance enhancement in stochastic pulse code systems using parallelism and redundancy

A 0.9V 960MHz CMOS radio front end employing a doubly balanced transconductance mixer

200 megasample per second 6 bit A/D converter

ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference

ESSCIRC '95: Twenty-first European Solid-State Circuits Conference

ESSCIRC '94: Twientieth European Solid-State Circuits Conference

ESSCIRC '93: Nineteenth European Solid-State Circuits Conference

ESSCIRC '92: Eighteenth European Solid-State Circuits conference

ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference

ESSCIRC '90: Sixteenth European Solid-State Circuits Conference

ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference

ESSCIRC '88: Fourteenth European Solid-State Circuits Conference

ESSCIRC '87: 13th European Solid-State Circuits Conference

ESSCIRC '86: Twelfth European Solid-State Circuits Conference

ESSCIRC '85: 11th European Solid-State Circuits Conference

ESSCIRC '84: Tenth European Solid-State Circuits Conference

ESSCIRC '83: Ninth European Solid-State Circuits Conference

ESSCIRC '82: Eighth European Solid-State Circuits Conference

ESSCIRC '81: 7th European Solid State Circuits Conference

ESSCIRC 80: 6th European Solid State Circuits Conference

Fifth European Solid State Circuits Conference - ESSCIRC 79

ESSCIRC 78: 4th European Solid State Circuits Conference - Digest of Technical Papers

ESSCIRC '77: 3rd European Solid State Circuits Conference

ESSCIRC 76: 2nd European Solid State Circuits Conference

1975 First European Solid State Circuits Conference (ESSCIRC)

Rapid design of complex DSP cores

Content Provider	IEEE Xplore Digital Library
Author	McCanny, J.V. Trainor, D. Hu, Y. Ding, T.J.
Copyright Year	1997
Description	Author affiliation: Queen's University of Belfast, Belfast, Nothern Ireland (McCanny, J.V.)
Abstract	Methods are presented for the rapid design of Digital Signal Processing chips which are based on the use of hierarchical VHDL libraries. These capture advanced, parameterised DSP architectures ("silicon intellectual property") at various levels of complexity. Resulting designs can be implemented in ASIC, PLD and FPGA technologies and are portable across many silicon foundries. Complex DSP designs are developed in a fraction of the time normally required and results compete very favourably with conventional methods. The approach is illustrated through its application to the design of FFT, DCT and Reed Solomon processors.
Starting Page	284
Ending Page	287
File Size	56976
Page Count	4
File Format	PDF
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-09-16
Access Restriction	Subscribed
Rights Holder	Editions Frontiers
Subject Keyword	Digital signal processing Digital signal processing chips Silicon Signal design Software libraries Intellectual property Application specific integrated circuits Field programmable gate arrays Foundries Discrete cosine transforms
Content Type	Text
Resource Type	Article

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