NDLI: 2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS

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2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

2014 IEEE International Solid-State Circuits Conference - Digest of Technical Papers [Copyright notice]

Table of contents

Foreword: Silicon systems bridging the cloud

The visuals supplement and the Saratoga Group — A 25-year history

Session 1 overview: Plenary session

1.1 Computing's energy problem (and what we can do about it)

1.2 Cloud 2.0 clients and connectivity — Technology and challenges

ISSCC Awards [17 awards]

1.3 How chips pave the Road to the Higgs particle and the attoworld beyond

1.4 The next generation of networked experiences

Session 2 overview: Ultra-high-speed transceivers and techniques: Wireline subcommittee

2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS

2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS

2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS

2.4 A 25Gb/s 5.8mW CMOS equalizer

2.5 A 0.25pJ/b 0.7V 16Gb/s 3-tap decision-feedback equalizer in 65nm CMOS

2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface

2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology

2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS

2.9 A Background calibration technique to control bandwidth in digital PLLs

Session 3 overview: RF techniques: RF subcommittee

3.1 polar antenna impedance detection and tuning for efficiency improvement in a 3G/4G CMOS Power Amplifier

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE

3.3 A transformer-coupled true-RMS power detector in 40nm CMOS

3.4 A dual-mode transformer-based doherty LTE power amplifier in 40nm CMOS

3.5 A 1.0-to-2.5GHz beamforming receiver with constant-G vector modulator consuming < 9mW per antenna element in 65nm CMOS

3.6 A noise-cancelling receiver with enhanced resilience to harmonic blockers

3.7 A fully integrated TV tuner front-end with 3.1dB NF, >+31dBm OIP3, >83dB HRR3/5 and >68dB HRR7

3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver

3.9 An RF-to-BB current-reuse wideband receiver with parallel N-path active/passive mixers and a single-MOS pole-zero LPF

Session 4 overview: DC-DC converters: Analog subcommittee

4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control

4.2 A 6A 40MHz four-phase ZDS hysteretic DC-DC converter with 118mV droop and 230ns response time for a 5A/5ns load transient

4.3 An 87%-peak-efficiency DVS-capable single-inductor 4-output DC-DC buck converter with ripple-based adaptive off-time control

4.4 A 10/30MHz Wide-duty-cycle-range buck converter with DDA-based Type-III compensator and fast reference-tracking responses for DVS applications

4.5 A 2-phase resonant switched-capacitor converter delivering 4.3W at $0.6W/mm^{2}$ with 85% efficiency

4.6 An 85%-efficiency fully integrated 15-ratio recursive switched-capacitor DC-DC converter with 0.1-to-2.2V output voltage range

4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering $3.7W/mm^{2}$ at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS

4.8 3-phase 6/1 switched-capacitor DC-DC boost converter providing 16V at 7mA and 70.3% efficiency in $1.1mm^{3}$

High-performance digital subcommittee

5.1 $POWER8^{TM}:$ A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the $POWER8^{TM}$ microprocessor

5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the $POWER8^{TM}$ microprocessor

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family

5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS

5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep

5.8 A 3GHz 64b ARM v8 processor in 40nm bulk CMOS technology

5.9 Haswell: A family of IA 22nm processors

Session 6 overview: Technologies for high-speed data networks: Technology directions subcommittee

6.1 memory and system architecture for 400Gb/s networking and beyond

6.2 High-capacity scalable optical communication for future Optical Transport Network

6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters

Session 7 overview: Image sensors: IMMD subcommittee

7.1 A 1/4-inch 8Mpixel CMOS image sensor with 3D backside-illuminated 1.12μm pixel with front-side deep-trench isolation and vertical transfer gate

7.2 243.3pJ/pixel bio-inspired time-stamp-based 2D optic flow sensor for artificial compound eyes

7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network

7.4 A 413×240-pixel sub-centimeter resolution Time-of-Flight CMOS image sensor with in-pixel background canceling using lateral-electric-field charge modulators

7.5 A 0.3mm-resolution Time-of-Flight CMOS range imager with column-gating clock-skew calibration

7.6 A 512×424 CMOS 3D Time-of-Flight image sensor with multi-frequency photo-demodulation up to 130MHz and 2GS/s ADC

Session 8 overview: Optical links and copper PHYs: Wireline subcommittee

8.1 A 6Gb/s transceiver with a nonlinear electronic dispersion compensator for directly modulated distributed-feedback lasers

8.2 A 12×5 two-dimensional optical I/O array for 600Gb/s chip-to-chip interconnect in 65nm CMOS

8.3 A power-scalable 7-tap FIR equalizer with tunable active delay line for 10-to-25Gb/s multi-mode fiber EDC in 28nm LP-CMOS

8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS

8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS

8.6 A full-duplex line driver for Gigabit Ethernet with rail-to-rail class-AB output stage in 28nm CMOS

8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS

8.8 An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS

8.9 A 40Gb/s VCSEL over-driving IC with group-delay-tunable pre-emphasis for optical interconnection

Session 9 overview: Low-power wireless: Wireless subcommittee

9.1 A self-calibrating NFC SoC with a triple-mode reconfigurable PLL and a single-path PICC-PCD receiver in 0.11μm CMOS

9.2 A 13.3mW 500Mb/s IR-UWB transceiver with link-margin enhancement technique for meter-range communications

9.3 A 1mW 1Mb/s 7.75-to-8.25GHz chirp-UWB transceiver with low peak-power transmission and fast synchronization capability

9.4 A 0.5V 1.15mW $0.2mm^{2}$ Sub-GHz ZigBee receiver supporting 433/860/915/960MHz ISM bands with zero external components

9.5 A 1.2nJ/b 2.4GHz receiver with a sliding-IF phase-to-digital converter for wireless personal/body-area networks

9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS

9.7 A 0.33nJ/b IEEE802.15.6/proprietary-MICS/ISM-band transceiver with scalable data-rate from 11kb/s to 4.5Mb/s for medical applications

9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications

Session 10 overview: Mobile Systems-on-Chip (SoCs): Energy-efficient digital subcommittee

10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications

10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores

10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor

10.4 A 1.22TOPS and 1.52mW/MHz augmented reality multi-core processor with neural network NoC for HMD applications

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications

10.6 A 0.74V 200μW multi-standard transceiver digital baseband in 40nm LP-CMOS for 2.4GHz Bluetooth Smart / ZigBee / IEEE 802.15.6 personal area networks

10.7 A 105GOPS $36mm^{2}$ heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS

10.8 A multi-standard 2G/3G/4G Cellular modem supporting carrier aggregation in 28nm CMOS

Session 11 overview: Data converter techniques: Data converters subcommittee

11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR

11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS

11.3 A 10b 0.6nW SAR ADC with data-dependent energy savings using LSB-first successive approximation

11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS

11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers

11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR

11.7 A 240mW 16b 3.2GS/s DAC in 65nm CMOS with <-80dBc IM3 up to 600MHz

Session 12 overview: Sensors, MEMS, and displays: IMMD subcommittee

12.1 3D ultrasonic gesture recognition

12.2 3D gesture-sensing system for interactive displays based on extended-range capacitive sensing

12.3 A 240Hz-reporting-rate 143×81 mutual-capacitance touch-sensing analog front-end IC with 37dB SNR for 1mm-diameter stylus

12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan

12.5 2D Coded-aperture-based ultra-compact capacitive touch-screen controller with 40 reconfigurable channels

12.6 A 160nW 63.9fJ/conversion-step capacitance-to-digital converter for ultra-low-power wireless sensor nodes

12.7 A 0.85V 600nW all-CMOS temperature sensor with an inaccuracy of ±0.4°C (3σ) from −40 to 125°C

12.8 A BJT-based CMOS temperature sensor with a $3.6pJ·K^{2}-resolution$ FoM

12.9 A $1.55×0.85mm^{2}$ 3ppm 1.0μA 32.768kHz MEMS-based oscillator

Session 13 overview: Advanced embedded memory: Memory subcommittee

13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology

13.2 A 14nm FinFET 128Mb 6T SRAM with V-enhancement techniques for low-power applications

13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists

13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current

13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-V applications

13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM

13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS

13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS

Session 14 overview: Millimeter-wave and terahertz techniques: RF subcommittee

14.1 A 0.9V 20.9dBm 22.3%-PAE E-band power amplifier with broadband parallel-series power combiner in 40nm CMOS

14.2 A 79GHz phase-modulated 4GHz-BW CW radar TX in 28nm CMOS

14.3 A Push-Pull mm-Wave power amplifier with <0.8° AM-PM distortion in 40nm CMOS

14.4 A Class F-1/F 24-to-31GHz power amplifier with 40.7% peak PAE, 15dBm OP, and 50mW P in 0.13μm SiGe BiCMOS

14.5 A 0.53THz reconfigurable source array with up to 1mW radiated power for terahertz imaging applications in 0.13μm SiGe BiCMOS

14.6 A scalable THz 2D phased array with +17dBm of EIRP at 338GHz in 65nm bulk CMOS

14.7 A 300GHz frequency synthesizer with 7.9% locking range in 90nm SiGe BiCMOS

14.8 A 247-to-263.5GHz VCO with 2.6mW peak output power and 1.14% DC-to-RF efficiency in 65nm Bulk CMOS

Session 15 overview: Digital PLLs: High-performance digital subcommittee

15.1 A $0.0066mm^{2}$ 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique

15.2 A $0.012mm^{2}$ 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider

15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO

15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS

Session 16 overview: SoC building blocks: High-performance digital subcommittee

16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

16.3 A 23Mb/s 23pJ/b fully synthesized true-random-number generator in 28nm and 65nm CMOS

16.4 0.6-to-1.0V $279μm^{2},$ 0.92μW temperature sensor with less than +3.2/-3.4°C error for on-chip dense thermal monitoring

Session 17 overview: Analog techniques: Analog subcommittee

17.1 An integrated 80V 45W class-D power amplifier with optimal-efficiency-tracking switching frequency regulation

17.2 A $0.0013mm^{2}$ 3.6μW nested-current-mirror single-stage amplifier driving 0.15-to-15nF capacitive loads with >62° phase margin

17.3 A 0.9V 6.3μW multistage amplifier driving 500pF capacitive load with 1.34MHz GBW

17.4 CMOS impedance analyzer for nanosamples investigation operating up to 150MHz with Sub-aF resolution

17.5 A $0.07mm^{2}$ 2-channel instrumentation amplifier with 0.1% gain matching in 0.16μm CMOS

17.6 Envelope modulator for multimode transmitters with AC-coupled multilevel regulators

17.7 A 1.89nW/0.15V self-charged XO for real-time clock generation

17.8 A 190nW 33kHz RC oscillator with ±0.21% temperature stability and 4ppm long-term stability

17.9 A 0.6V 70MHz $4^{th}-order$ continuous-time Butterworth filter with 55.8dB SNR, 60dB THD at +2.8dBm output signal power

17.10 0.65V-input-voltage 0.6V-output-voltage 30ppm/°C low-dropout regulator with embedded voltage reference for low-power biomedical systems

17.11 A 0.65ns-response-time 3.01ps FOM fully-integrated low-dropout regulator with full-spectrum power-supply-rejection for wideband communication systems

Session 18 overview: Biomedical systems for improved quality of life: Technology directions subcommittee

18.1 A 1V 3mA 2.4GHz wireless digital audio communication SoC for hearing-aid applications in 0.18μm CMOS

18.2 A fully-implantable cochlear implant SoC with piezoelectric middle-ear sensor and energy-efficient stimulation in 0.18μm HVCMOS

18.3 A multi-parameter signal-acquisition SoC for connected personal health applications

18.4 A 4.9mΩ-sensitivity mobile electrical impedance tomography IC for early breast-cancer detection system

18.5 A 2.14mW EEG neuro-feedback processor with transcranial electrical stimulation for mental-health management

18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications

18.7 A remotely controlled locomotive IC driven by electrolytic bubbles and wireless powering

Session 19 overview: Nonvolatile memory solutions: Memory subcommittee

19.1 A 128Gb MLC NAND-Flash device using 16nm planar cell

19.2 A $93.4mm^{2}$ 64Gb MLC NAND-flash memory with 16nm CMOS technology

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme

19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming

19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers

19.7 A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology

Session 20 overview: Wireless systems: Wireless subcommittee

20.1 A 40nm CMOS receiver for 60GHz discrete-carrier indoor localization achieving mm-precision at 4m range

20.2 A 16TX/16RX 60GHz 802.11ad chipset with single coaxial interface and polarization diversity

20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication

20.5 A 40nm dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s over-the-air throughput

20.6 A blocker-resilient wideband receiver with low-noise active two-point cancellation of >0dBm TX leakage and TX noise in RX band for FDD/Co-existence

20.7 A multi-band inductor-less SAW-less 2G/3G-TD-SCDMA cellular receiver in 40nm CMOS

20.8 A 20mW GSM/WCDMA receiver with RF channel selection

Session 21 overview: Frequency generation techniques: RF subcommittee

21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC

21.2 A 2.3GHz fractional-N dividerless phase-locked loop with −112dBc/Hz in-band phase noise

21.3 A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS

21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS

21.5 A 3.24-to-8.45GHz low-phase-noise mode-switching oscillator

21.6 A 2.4-to-5.3GHz dual-core CMOS VCO with concentric 8-shaped coils

21.7 A 1.8mW PLL-free channelized 2.4GHz ZigBee receiver utilizing fixed-LO temperature-compensated FBAR resonator

21.8 A pulling mitigation technique for direct-conversion transmitters

Session 22 overview: High-speed data converters: Data converters subcommittee

22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS

22.2 A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI

22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology

22.4 A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration

22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS

22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers

22.7 A 14b 4.6GS/s RF DAC in 0.18μm CMOS for cable head-end systems

Session 23 overview: Energy harvesting: Analog subcommittee

23.1 A 0.15V-input energy-harvesting charge pump with switching body biasing and adaptive dead-time for efficiency improvement

23.2 A 1.1nW energy harvesting system with 544pW quiescent power for next-generation implants

23.3 A 3nW fully integrated energy harvester based on self-oscillating switched-capacitor DC-DC converter

23.4 Dual-source single-inductor 0.18μm CMOS charger-supply with nested hysteretic and adaptive on-time PWM control

23.5 An energy pile-up resonance circuit extracting maximum 422% energy from piezoelectric material in a dual-source energy-harvesting interface

23.6 A 43V 400mW-to-21W global-search-based photovoltaic energy harvester with 350μs transient time, 99.9% MPPT efficiency, and 94% power efficiency

23.7 Self-powered 30μW-to-10mW Piezoelectric energy-harvesting system with 9.09ms/V maximum power point tracking time

23.8 A 34V charge pump in 65nm bulk CMOS technology

Session 24 overview: Integrated biomedical systems: IMMD subcommittee

24.1 A miniaturized 64-channel 225μW wireless electrocorticographic neural sensor

24.2 A power-efficient switched-capacitor stimulating system for electrical/optical deep-brain stimulation

24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis

24.4 A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction

24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia

24.6 A CMOS micro-flow cytometer for magnetic label detection and classification

24.7 A 60nV/√Hz 15-channel digital active electrode system for portable biopotential signal acquisition

24.8 An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area

Session 25 overview: High-bandwidth low-power DRAM and I/O: Memory subcommittee

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector

Session 26 overview: Energy-efficient dense interconnects: Wireline subcommittee

26.1 A 130mW 20Gb/s half-duplex serial link in 28nm CMOS

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS

26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology

26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS

26.5 An 8-to-16Gb/s 0.65-to-1.05pJ/b 2-tap impedance-modulated voltage-mode transmitter with fast power-state transitioning in 65nm CMOS

26.6 A 2.667Gb/s DDR3 memory interface with asymmetric ODT on wirebond package and single-side-mounted PCB

Session 27 overview: Energy-efficient digital circuits: Energy-efficient digital subcommittee

27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding F tracking

27.2 A 6mW 5K-Word real-time speech recognizer using WFST models

27.3 A 210mV 5MHz variation-resilient near-threshold JPEG encoder in 40nm CMOS

27.4 A 0.75-million-point fourier-transform chip for frequency-sparse signals

27.5 A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing

27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder

27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI

27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications

Session 28 overview: Mixed-signal techniques for wireless: Wireless subcommittee

28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS

28.2 A $0.29mm^{2}$ frequency synthesizer in 40nm CMOS with 0.19ps jitter and <-100dBc reference spur for 802.11ac

28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS

Session 29 overview: Data converters for wireless systems: Data converters subcommittee

29.1 A 5mW CT ΔΣ ADC with embedded $2^{nd}-order$ active filter and VGA achieving 82dB DR in 2MHz BW

29.2 A 235mW CT 0-3 MASH ADC achieving −167dBFS/Hz NSD with 53MHz BW

29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration

Session 30 overview: Technologies for next-generation systems: Technology directions subcommittee

30.1 8b Thin-film microprocessor using a hybrid oxide-organic complementary technology with inkjet-printed $P^{2}ROM$ memory

30.2 Digital PWM-driven AMOLED display on flex reducing static power consumption

30.3 Organic-transistor-based 2kV ESD-tolerant flexible wet sensor sheet for biomedical applications with wireless power and data transmission using 13.56MHz magnetic resonance

30.4 A 13.56MHz RFID tag with active envelope detection in an organic complementary TFT technology

30.5 A GaN 3×3 matrix converter chipset with Drive-by-Microwave technologies

30.6 An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%

30.7 A 60Mb/s wideband BCC transceiver with 150pJ/b RX and 31pJ/b TX for emerging wearable applications

30.8 A 30GS/s double-switching track-and-hold amplifier with 19dBm IIP3 in an InP BiCMOS technology

30.9 Normally-off computing with crystalline InGaZnO-based FPGA

30.10 A 1TOPS/W analog deep machine-learning engine with floating-gate storage in 0.13μm CMOS

Tutorials [10 abstracts]

F1: Digitally assisted analog and analog-assisted digital in high-performance scaled CMOS process

F2: 3D stacking technologies for image sensors and memories

F3: Adaptive design techniques for energy efficiency

F4: Mm-Wave advances for active safety and communication systems

F5: Low-power radios for sensor networks

F6: Energy-efficient I/O design for next-generation systems

Student research preview

ES2: Data centers to support tomorrow's cloud

EP1: Next-generation networked systems-challenges for silicon

ES3: Wearable wellness devices: Fashion, health, and informatics

EP2: Anatomy of innovation: Bug or feature?

EP3: Perspectives on the future of semiconductor innovation

SC1: Biomedical and sensor interface circuits

Index to authors

Executive committee

International technical program committee

Call for papers

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

2012 IEEE International Solid-State Circuits Conference

2011 IEEE International Solid-State Circuits Conference

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)

2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)

1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

Proceedings ISSCC '95 - International Solid-State Circuits Conference

Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94

1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers

1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers

1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1990 37th IEEE International Conference on Solid-State Circuits

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1975 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1974 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1973 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1972 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1971 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1970 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1969 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1968 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1967 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1966 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1965 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1964 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1962 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1961 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1960 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1959 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1958 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1957 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1956 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1955 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Ping-Chuan Chiang Hao-Wei Hung Hsiang-Yun Chu Guan-Sing Chen Jri Lee
Copyright Year	2014
Description	Author affiliation: Nat. Taiwan Univ., Taipei, Taiwan (Ping-Chuan Chiang; Hao-Wei Hung; Hsiang-Yun Chu; Guan-Sing Chen; Jri Lee)
Abstract	Recent research indicates that data-link transceivers running at or below 40Gb/s are practical to implement in CMOS technology [1]. However, next-generation datacom and telecom systems require transceivers to operate at even higher data rates. For example, a 400Gb/s Ethernet system may need 8×50Gb/s PAM2 (NRZ) or PAM4 channels [2]. This paper introduces fully integrated solutions for NRZ and PAM4 transmitters. The 60Gb/s operating speed demonstrates sufficient bandwidth even for standards with coding overhead.
Starting Page	42
Ending Page	43
File Size	1810718
Page Count	2
File Format	PDF
ISBN	9781479909186
ISSN	01936530
e-ISBN	9781479909209
DOI	10.1109/ISSCC.2014.6757329
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-02-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Transmitters Phase locked loops Optical signal processing CMOS integrated circuits Synchronization Power transmission lines
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Electronic, Optical and Magnetic Materials

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