NDLI: Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clock-gating scheme in leakage dominant era

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No exponential is forever: but "Forever" can be delayed! [semiconductor industry]

Perspectives on power-aware electronics

Bridging the gap between the digital and real worlds: the expanding role of analog interface technologies

A fully-integrated 0.13/spl mu/m CMOS mixed-signal SoC for DVD player applications

A single-chip MPEG2 CODEC for DVD+RW

A 160 mW, 80 nA standby, MPEG-4 audiovisual LSI with 16 Mb embedded DRAM and a 5 GOPS adaptive post filter

A 210mW graphics LSI implementing full 3D pipeline with 264Mtexels/s texturing for mobile multimedia applications

Image processor capable of block-noise-free JPEG2000 compression with 30 frames/s for digital camera applications

A 51.2 GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 4-way VLIW processing elements

A 1 GOPS reconfigurable signal processing IC with embedded FPGA and 3-port 1.2 GB/s flash memory subsystem

A 1.5V 1mA 80dB passive /spl Sigma//spl Delta/ ADC in 0.13/spl mu/m digital CMOS process

A 114 dB 68 mW chopper-stabilized stereo multi-bit audio A/D converter

A 1.2-V dual-mode WCDMA/GPRS /spl Sigma//spl Delta/ modulator

A tri-mode continuous-time /spl Sigma//spl Delta/ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver

A continuous-time /spl Sigma//spl Delta/ modulator with 88dB dynamic range and 1.1MHz signal bandwidth

A 4.4mW 76dB complex /spl Sigma//spl Delta/ ADC for Bluetooth receivers

A dual channel /spl Sigma//spl Delta/ ADC with 40MHz aggregate signal bandwidth

A 10Gb/s/ch 50mW 120/spl times/130/spl mu/m/sup 2/ clock and data recovery circuit

A CMOS multi-channel 10Gb/s transceiver

A second-order semi-digital clock recovery circuit based on injection locking

A 2.5-10Gb/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization

8Gb/s differential simultaneous bidirectional link with 4mV 9ps waveform capture diagnostic capability

Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell

A 2.7 Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems

A dual mode 802.11b/Bluetooth radio in 0.35/spl mu/m CMOS

A 2.4GHz dual-mode 0.18/spl mu/m CMOS transceiver for Bluetooth and 802.11b

A 43mW Bluetooth transceiver with -91dBm sensitivity

An experimental coin-sized radio for extremely low power WPAN (IEEE802.15.4) application at 2.4GHz

A single-chip CMOS Bluetooth transceiver with 1.5MHz IF and direct modulation transmitter

A low power CMOS Bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator

CMOS differential LC oscillator with suppressed up-converted flicker noise

Dynamic-sleep transistor and body bias for active leakage power control of microprocessors

A shared-well dual-supply-voltage 64-bit ALU

A 0.5V, 400MHz, V/sub 00/-hopping processor with zero-V/sub TH/ FD-SOI technology

An autonomous decentralized low-power system with adaptive-universal control for a chip multi-processor

A 400MHz 183mW microcontroller in body-tied SOI technology

A 3.5GHz 32mW 150nm multiphase clock generator for high-performance microprocessors

A 0.3V 3.6GHz 0.3mW frequency divider with differential ED-CMOS/SOI circuit technology

A 9/spl mu/W 50MHz 32b adder using a self-adjusted forward body bias in SoCs

A 16b 400MS/s DAC with <-80dBc IMD to 300MHz and <-160dBm/Hz noise power spectral density

A 1.5 V 14 b 100 MS/s self-calibrated DAC

A 4/spl times/40 W digital input class-AB power DAC with 100 dB dynamic range

A 500 MHz CMOS anti-alias filter using feed-forward op-amps with local common-mode feedback

A class D output stage with zero dead time

A baseband gain-controlled amplifier with a linear-in-dB gain range from 14 dB to 76 dB and a fixed corner frequency DC offset canceler

A 3 A 20 MHz BiCMOS/DMOS power operational amplifier: a structural design approach

A high performance SSL IPSEC protocol aware security processor

A single-chip 802.11a MAC/PHY with a 32 b RISC processor

Dual antenna UMTS mobile station transceiver ASIC for 2 Mb/s data rate

A 13.3Mb/s 0.35/spl mu/m CMOS analog turbo decoder IC with a configurable interleaver

A 24Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless

A scalable 8.7nJ/bit 75.6Mb/s parallel concatenated convolutional (turbo-) CODEC

A programmable turbo decoder for multiple 3G wireless standards

Filling the gap between system conception and silicon/software implementation

Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

Ultra-high resolution image capturing and processing for digital cinematography

A CPU on a glass substrate using CG-silicon TFTs

Timekeeping techniques for predicting and optimizing memory behavior

A wire-delay scalable microprocessor architecture for high performance systems

A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network

A 20-input 20-output 12.5Gb/s SiGe cross-point switch with less than 2ps RMS jitter

A 30Gb/s 1:4 demultiplexer in 0.12/spl mu/m CMOS

A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18/spl mu/m CMOS technology

Differential 4-tap and 7-tap transverse filters in SiGe for 10Gb/s multimode fiber optic link equalization

Broadband ESD protection circuits in CMOS technology

A 1.6Gb/s/pair electromagnetically coupled multidrop bus using modulated signaling

1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme

10Gb/s limiting amplifier and laser/modulator driver in 0.18/spl mu/m CMOS technology

A CMOS chip for individual cell manipulation and detection

Low-power interface circuits for bio-implantable microsystems

136/spl mu/W/channel autonomous strain gauge datalogger

A high density conduction based micro-DNA-identification array fabricated in a CMOS compatible process

A CMOS temperature sensor with a 3/spl sigma/ inaccuracy of /spl plusmn/0.5/spl deg/C from -50/spl deg/C to 120/spl deg/C

A multi-step electromechanical /spl Sigma//spl Delta/ converter for micro-g capacitive accelerometers

Integrated multiple-device IMU system with continuous-time sensing circuitry

An above-IC RF-MEMS switch

An active range finder with the capability of -18dB SBR, 48dB dynamic range and 120 /spl times/ 110 pixel resolution

A 0.18 /spl mu/m high dynamic range NTSC/PAL imaging system-on-chip with embedded DRAM frame buffer

A capacitive hybrid flip-chip ASIC and sensor for fingerprint, navigation and pointer detection

A 1 1/4 inch 8.3M pixel digital output CMOS APS for UDTV application

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Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clock-gating scheme in leakage dominant era

Self-corrective device and architecture to ensure LSI operation at 0.5 V using bulk dynamic threshold MOSFET with a self-adaptive power supply

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A CMOS up-conversion receiver front-end for cable and terrestrial DTV applications

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60GHz and 76GHz oscillators in 0.25/spl mu/m SiGe:C BiCMOS

A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST

A 320ps access, 3GHz cycle, 144Kb SRAM macro in 90nm CMOS technology using an all-stage reset control signal generator

A 1.5V 1.7ns 4k /spl times/ 32 SRAM with a fully-differential auto-power-down current sense amplifier

A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25/spl mu/m CMOS

A multi-context 6.4Gb/s/channel on-chip communication network using 0.18/spl mu/m Flash-EEPROM switches and elastic interconnects

An 800MHz star-connected on-chip network for application to systems on a chip

A variable-kernel flash-convolution image filtering processor

A 250MHz direct digital frequency synthesizer with /spl Sigma//spl Delta/ noise shaping

Highlights of DAC

Circuits in emerging technolgoies

How far can integration go for 3G cellphones?

Foreword - power-aware systems

E1 analog IP - stairway to SoC heaven?

E2 will MEMS, imagers, and displays, be key to the growth of the IC industry?

E3 good, bad, ugly - 50 years of memory evolution. what next?

E4 future mobile phones; a beautiful dream or smoke in LSI technology?

E5 fineline prototyping: breaking new ground or breaking the bank?

E6 SoC: DOA? RIP?

Short course - system-on-a-chip design

Workshop on analog telecom and circuit concepts

Workshop on implications of near-limit CMOS on circuits and applications

Workshop on microprocessor design in the power-constrained era

Workshop on gigahertz-radio front ends

Executive Committee

US program committee

European Program Committee

Far East Program Committee

ISSCC 2004 call for papers

ISSCC 2004 timetable

Table of contents ISSCC 50th anniversary supplement 1954-2003

The international solid-state circuits community and its annual conference - genesis and first decade

ISSCC - the later years

50 years of ISSCC technical and general chairs

A history of the Far-East program committee at ISSCC

A history of the European program committee at ISSCC

History of papers at ISSCC

A half-century of press relations at ISSCC

50 years of analog development at ISSCC

50 years of communication circuits at ISSCC

50 years of signal processing at ISSCC

50 years of digital logic and microprocessors at ISSCC

50 years of memories at ISSCC

50 years of solid-state image sensors at ISSCC

50 years of sensors (and MEMS) at ISSCC

Forty years of feature-size predictions (1962-2002)

ISSCC 2003 / 50th anniversary photos

ISSCC 50-year anniversary author honor roll

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)

2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)

1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

Proceedings ISSCC '95 - International Solid-State Circuits Conference

Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94

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1965 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1964 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1962 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1961 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1960 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1959 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1958 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1957 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1956 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1955 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clock-gating scheme in leakage dominant era

Content Provider	IEEE Xplore Digital Library
Author	Kyeong-Sik Min Kawaguchi, H. Sakurai, T.
Copyright Year	2003
Description	Author affiliation: Univ. of Tokyo, Japan (Kyeong-Sik Min; Kawaguchi, H.; Sakurai, T.)
Abstract	A block activation/deactivation technique uses zigzag super cut-off CMOS to improve wake up time by 8/spl times/ in 0.6 /spl mu/m CMOS versus super cutoff CMOS. Our clock-gating substitute achieves a 200 ps wake-up time and 3 orders of magnitude leakage reduction for leakage dominant LSI's.
Sponsorship	IEEE Solid-State Circuits Soc. IEEE San Francisco Sect., Bay Area Council Univ. PA
Starting Page	400
Ending Page	502
File Size	592066
Page Count	103
File Format	PDF
ISBN	0780377079
ISSN	01936530
DOI	10.1109/ISSCC.2003.1234355
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-02-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage control Clocks Switches Energy consumption Stress Delay Degradation Power generation Combinational circuits Signal restoration
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Electronic, Optical and Magnetic Materials

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