NDLI: Ultra-thin-film SOI technology and its application to next generation CMOS devices

Content Provider	IEEE Xplore Digital Library
Author	Kawamura, S.
Copyright Year	1993
Description	Author affiliation: LSI Process Dev. Div., Fujitsu Labs. Ltd., Kawasaki, Japan (Kawamura, S.)
Abstract	Although silicon-on-insulator (SOI) technology has been developed for over a quarter of a century, it has been in use only in specialized niche applications such as space and defense electronics systems. This is mainly because SOI manufacturing yields have been considered to be lower than their conventional bulk counterparts. In spite of the recent development of fully depleted SOI devices fabricated in ultra-thin silicon on insulator films which are considered very attractive for high-speed submicron ULSI applications because of the reduced short-channel effect in addition to the generic SOI advantages of latchup immunity and reduced parasitic capacitances, several problems which should be overcome still remain, both in materials and device technology as well as in manufacturing aspects,before thin-film SOI can be considered mainstream. The major potential application for ultra-thin SOI films is quarter micron CMOS devices for advanced logic circuits. It is anticipated that CMOS devices having design rules of 0.25 /spl mu/m or less will be in mass production by the end of this century, and conventional bulk silicon seems to be unsuitable for such ULSI devices mainly because of severe short channel effects. Instead, thin-film SOI with fully depleted silicon films is expected to be an alternative.
Starting Page	6
Ending Page	7
File Size	140596
Page Count	2
File Format	PDF
ISBN	0780313461
DOI	10.1109/SOI.1993.344613
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-10-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon on insulator technology Space technology Manufacturing Semiconductor films Ultra large scale integration Semiconductor thin films Thin film circuits Parasitic capacitance CMOS technology Thin film devices
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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