NDLI: Effect of back gate on parasitic bipolar effect in FD SOI MOSFETs

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2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

Welcome to the 2014 IEEE SOI-3DI-subthreshold microelectronics technology unified conference (S3S)

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The role of the cloud in Machine to Machine & Internet of Things computing best practices, key insights and guidance to connecting devices to the cloud

Advanced High K/Metal SOI technologies for 32nm and beyond

A 361nA thermal run-away immune VBB generator using dynamic substrate controlled charge pump for ultra low sleep current logic on 65nm SOTB

A 53µW −82dBm sensitivity 920MHz OOK receiver design using bias switch technique on 65nm SOTB CMOS technology

SOI FinFET versus bulk FinFET for 10nm and below

High mobility w-gate nanowire P-FET on cSGOI substrates obtained by Ge enrichment technique

Dielectric isolated FinFETs on bulk substrate

Elastic relaxation in intrinsically-strained Fins: Simulations, physical and electrical characterization

Toward robust subthreshold circuit design - Variability and soft error perspective

Energy efficiency benefits of subthreshold-optimized transistors for digital logic

Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

A reduced-memory FIR filter using approximate coefficients for ultra-low power SoCs

Monolithic 3D integration: A powerful alternative to classical 2D scaling

Design challenges and solutions for ultra-high-density monolithic 3D ICs

3D memory with shared lithography steps: The memory industry's plan to “cram more components onto integrated circuits”

Monolithic 3D integration in a CMOS process flow

Monolithic 3D integration advances and challenges: From technology to system levels

Performance assessment of ULP analog/RF MOSFET architectures

Effects of back-gate bias on switched-capacitor DC-DC converters in UTBB FD-SOI

An optimal probing method of pre-bond TSV fault identification in 3D stacked ICs

Power supply voltage detection and clamping circuit for 3-D integrated circuits

Study of fin-tunnel FETs with doped pocket as capacitor-less 1T DRAM

On the cryogenic performance of ultra-low-loss, wideband SPDT RF switches designed in a 180 nm SOI-CMOS technology

Analog performance of short-channel asymmetric self-cascode of junctionless nanowire nMOS transistors

Multi-threshold design methodology of stacked Si-nanowire FETs

Analog building block design in 14nm FinFET using inversion coefficient

28 nm FD SOI Technology Platform RF FoM

An SOI based integrated gate-drivers for automotive application

Effect of back gate on parasitic bipolar effect in FD SOI MOSFETs

High temperature performance of flexible SOI FinFETs with sub-20 nm fins

UTBB/FDSOI: Reasons for a success

Piezoresistivity in unstrained and strained SOI MOSFETs

nFET FDSOI activated by low temperature solid phase epitaxial regrowth: Optimization guidelines

In depth characterization of hole transport in 14nm FD-SOI pMOS devices

Influence of underlap on UTBB SOI MOSFETs in dynamic threshold mode

Near-0.1V ultra-low voltage operation of SOTB 1M logic gates

Performance prediction for multiple-threshold 7nm-FinFET-based circuits operating in multiple voltage regimes using a cross-layer simulation framework

A cross-layer design framework and comparative analysis of SRAM cells and cache memories using 7nm FinFET devices

Efficient ultra low power rectification at 13.56 MHz for a 10 µA load current

Experimental model of adaptive body biasing for energy efficiency in 28nm UTBB FD-SOI

UTBB FD-SOI front- and back-gate coupling aware random telegraph signal impact analysis on a 6T SRAM

Mixed-single well 8T SRAM bitcell for wide voltage range in 28nm FDSOI

A tunnel-FET SRAM array for energy-efficient embedded memory blocks in reconfigurable computing platforms

Impacts of work function variation and line-edge roughness on TFET and FinFET devices and logic circuits

OxRAM-based pulsed latch for non-volatile flip-flop in 28nm FDSOI

Electron-hole bilayer deep subthermal electronic switch: Physics, promise and challenges

Beyond TFET: Alternative mechanisms for CMOS-compatible sharp-switching devices

A2RAM: Low-power 1T-DRAM memory cells compatible with planar and 3D SOI substrates

Bias-flip technique for frequency tuning of piezo-electric energy harvesting devices: Experimental verification

Adaptive subthreshold switched capacitor voltage boost for thermoelectric generation

SOI substrate solutions for recent advanced device applications

The role of radiation effects in SOI technology development

A very low power CMOS 28FDSOI programmable fractional frequency divider for Wifi-WiGig

Recent advances and future trends in SOI for RF applications

SEU Hardening: Incorporating an Extreme Low Power Bitcell Design (SHIELD)

Impact of ultra-low voltages on single-event transients and pulse quenching

Compensation of total ionizing dose effects in ULV SoCs through adaptive voltage scaling

Near-threshold voltage operation of a nonvolatile SRAM cell based on pseudo-spin-FinFET architecture

More than an order of magnitude energy improvement of FPGA by combining 0.4V operation and Multi-Vt optimization of 20k body bias domains

Monolithic IC integration key alignment aspects for high process yield

New precision alignment methodology for CMOS wafer bonding

Precision bonders - A game changer for monolithic 3D

Fully functional fine-grain vertically integrated 3D focal plane neuromorphic processor

Smart co-integration of light sensitive layers with FDSOI transistors for More than Moore applications

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

A 262nW analog front end with a digitally-assisted low noise amplifier for batteryless EEG acquisition

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Effect of back gate on parasitic bipolar effect in FD SOI MOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Liu, Fanyu Ionica, Irina Bawedin, Maryline Cristoloveanu, Sorin
Copyright Year	2014
Description	Author affiliation: IMEP-LAHC, MINATEC, 38016 Grenoble, France (Liu, Fanyu; Ionica, Irina; Cristoloveanu, Sorin) \|\| Université Montpellier II, 34095, France (Bawedin, Maryline)
Abstract	In short-channel fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs, the drain leakage current is enhanced by the parasitic bipolar transistor. The parasitic bipolar effect is induced by band-to-band tunneling and floating-body effects. It strongly depends on film thickness and back-gate voltage. We show experimentally the possibility to reduce the parasitic bipolar effect by biasing the back gate (ground plane). Based on devices simulations, we discuss the origin of the bipolar action, its suppression and the possible applications.
Starting Page	1
Ending Page	2
File Size	672784
Page Count	2
File Format	PDF
ISBN	9781479974399
DOI	10.1109/S3S.2014.7028210
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Junctions MOSFET Leakage currents Silicon-on-insulator Tunneling Bipolar transistors band-to-band tunneling parasitic bipolar effect back gate FD SOI
Content Type	Text
Resource Type	Article

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