NDLI: Self-heating enhanced impact ionization in SOI MOSFETs

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2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207)

Advantages and challenges of high performance CMOS on SOI

Status and technology of SOI substrate material

Nano-scale silicon MOSFET: towards non-traditional and quantum devices

Atomic-layer cleaving with Si/sub x/Ge/sub y/ strain layers for fabrication of Si and Ge-rich SOI device layers

SiGe-On-Insulator (SGOI): substrate preparation and MOSFET fabrication for electron mobility evaluation

BOX layer formation by oxygen precipitation at implantation damage of light ions

Application of laser scattering and optical defect detection methods to SIMOX-SOI wafers

Defect detection on SOI wafers using laser scattering tools

Design analysis of thin-body silicide source/drain devices

0.11 /spl mu/m fully-depleted SOI CMOS devices with 26 nm silicon layer fabricated by bulk compatible process

Explaining the reduced floating body effects in narrow channel SOI MOSFETs

f/sub T/ variation caused by channel width effects in ladder gate structure for RF SOI MOSFETs

Exploitation of volume inversion in optimal DG MOSFET design

Self-heating enhanced impact ionization in SOI MOSFETs

Comparison of boron diffusion profiles in ultra thin SOI structures

Gas cluster ion beam processing of SOI surfaces for improved gate oxide integrity

Characterization of SOI wafers by temporal decay measurement of condensate luminescence

FTIR dosimetry mapping of as-implanted SIMOX wafers

New implant equipment for the production of commercial SOI substrates

Effect of implant dose and energy on formation of thin SOI structure in SIMOX using water plasma

Ultra-thin film fully-depleted SOI CMOS with raised G/S/D device architecture for sub-100 nm applications

Recessed multi-gate SOI MOSFET in deep decananometer regime

Simulations of ultrathin SOI with quantum transport models

Phenomenalistic reconsideration of Hooge parameter in buried-channel metal-oxide-semiconductor field-effect transistors

Threshold voltage fluctuation analysis in dynamic threshold MOSFET based on charge-sharing

80nm SOI CMOS parameter extraction for BSIMPD

Measurement of history effect in PD/SOI single-ended CPL circuit

Multiple output domino logic (MODL) in SOI

Implementation of a multi-bit /spl utri//spl Sigma/ A/DC without a correction RAM

Novel 0.8 V true-single-phase-clocking (TSPC) latches using PD-SOI DTMOS techniques for low-voltage CMOS VLSI circuits

5+ GHz CMOS prescaler

High resistive ELTRAN/sup (R)/ SOI-Epi/sup TM/ wafers for RF application

A parallel between silicon splitting kinetics study and IR absorption analysis

Partial trench isolated body-tied (PTIBT) structure for SOI applications

Fabrication & characterization of Schottky junction transistors

A picosecond photodetector on SOI structures for 0.4 /spl mu/m band

A novel five-channel NMOSFET using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE)

300 Mbps level converters for 0.5 V system LSIs using FD/PD-SOI technology

Investigation of SOI sensitivity to SEU-Influence of the buried oxide coupling effect

A novel shallow trench isolation technology using LPCVD MTO/SiN liner in SOI wafer

Reduction of STI/active stress on 0.18 /spl mu/m SOI devices through modification of STI process

Characterization and simulation of STI isolation for 0.1 /spl mu/m partially-depleted SOI devices

Ar implantation effects in SOI NMOSFET's under low voltage operation

Metal gates for advanced sub-80-nm SOI CMOS technology

Double-gate SOI MOSFET fabrication from bulk silicon wafer

A low-cell-stress SOI SRAM sensing technique

0.15 /spl mu/m SOI DRAM technology incorporating sub-volt dynamic threshold devices for embedded mixed-signal & RF circuits

Novel circuits to improve SRAM performance in PD/SOI technology

Assessing circuit level impact of self-heating in 0.13 /spl mu/m SOI CMOS

Circuit style comparison based on the variable voltage transfer characteristic and floating /spl beta/ ratio concept of partially depleted SOI

Layout optimization of cascode RF SOI transistors

New substrate-crosstalk reduction structure using SOI substrate [for one-chip transceiver IC]

Lateral gate-all-around (GAA) poly-Si transistors

Quasi-planar FinFETs with selectively grown germanium raised source/drain

Characterization of fully depleted SOI transistors after removal of the silicon substrate

Comparison of gate structures for short-channel SOI MOSFETs

Multi-layers with buried structures (MLBS): an approach to three-dimensional integration

Single-mode silicon optical switch with T-shape SiO/sub 2/ waveguide as a control gate

Worst case conditions for hot-carrier induced degradation of sub-100 nm partially depleted SOI MOSFET's

The role of externally applied body-bias on the hot-carrier degradation of partially depleted SOI N-MOSFETs

Radiation induced degradation of SOI n-channel LDMOSFETs

Modeling the gated-diode response of an irradiated SOI back-channel interface

Study of relevance of the SIMOX defect type on yield of radiation-tolerant device test structures

Evaluating manufacturability of radiation-hardened SOI substrates

Comparison of bulk vs SOI for low power low voltage CMOS imager

A tri-state body charge modulated SOI sense amplifier

A novel CMOS SOI unbalanced Mach-Zehnder interferometer: from design and simulations to fabrication and characterization

Design of a SOI fully integrated 1 V, 2.5 GHz front-end receiver

Characteristics of RF power amplifiers by 0.5 /spl mu/m SOS CMOS process

A 0.5-1 V MTCMOS/SIMOX ROM macro with low-V/sub th/ memory cells

Reconsideration of off-leakage current estimation of sub-100-nm SOI MOSFETs and device selection for applications

Enhanced subthreshold leakage current due to impact ionization in deep sub-100nm N-channel double-gate MOSFETs

Double-gate SOI MOSFETs with asymmetrical configuration

Nanoscale SOI ballistic MOSFETs: an impending power crisis

A SOI capacitor-less 1T-DRAM concept

Unibond(R) SOI wafers for ultra-thin films applications

2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125)

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)

1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199)

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Proceedings. IEEE International SOI Conference

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Self-heating enhanced impact ionization in SOI MOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Su, P. Goto, K. Sugii, T. Hu, C.
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA (Su, P.)
Abstract	Impact ionization (II) originates from energetic carriers in the channel. The II current is not only a monitor of device reliability, but also affects the current drive of partially-depleted (PD) SOI transistors by charging up the floating body and hence varying the threshold voltage. Due to the low thermal conductivity of buried oxide, SOI MOSFETs are susceptible to the local thermal heating generated in the channel. This SOI-specific self-heating effect (SHE) provides a source for carrier heating, which may determine impact ionization. In this paper we report an enhanced impact-ionization phenomenon caused by SHE in SOI MOSFETs.
Sponsorship	IEEE Electron Devices Soc
Starting Page	31
Ending Page	32
File Size	187850
Page Count	2
File Format	PDF
ISBN	0780367391
ISSN	1078621X
DOI	10.1109/SOIC.2001.957970
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-10-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Impact ionization MOSFETs Thermal conductivity Heating Temperature sensors Energy consumption Current measurement Logic circuits Circuit simulation Temperature dependence
Content Type	Text
Resource Type	Article

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