NDLI: 64 Mbit SOI-DRAM technologies using body-contacted (BC) structure

Content Provider	IEEE Xplore Digital Library
Author	Yo-Hwan Koh Jin-Hyeok Choi Ji-Woon Yang Myung-Hee Nam Won-Chang Lee Jong-Wook Lee Min-Rok Oh
Copyright Year	1997
Description	Author affiliation: Adv. Device Dept., Hyundai Electron. Ind. Co. Ltd., Kyoungki, South Korea (Yo-Hwan Koh)
Abstract	Summary form only given. Recently, DRAMs using SOI substrates have been widely needed because of their inherent high speed low power characteristics due to small junction capacitances. However, the floating body effect is the most serious problem. The floating body can cause dynamic retention time problems in DRAMs, and a leakage problem due to a small drain-to-source breakdown voltage. In this work, a Body-Contacted (BC) SOI MOSFET structure with no floating body effect is successfully applied to a 64M SOI DRAM. The layout, process steps and the operation voltage are completely compatible with the bulk MOSFET process. We evaluated the transistor characteristics and the chip performances.
Starting Page	170
Ending Page	171
File Size	215092
Page Count	2
File Format	PDF
ISBN	078033938X
ISSN	1078621X
DOI	10.1109/SOI.1997.634987
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET circuits Random access memory Silicon Semiconductor films CMOSFETs Substrates Voltage Capacitance measurement Delay effects Research and development
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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