NDLI: Modification of parasitic edge leakage in LOCOS-isolated SOI MOSFETS using back-gate stress

Content Provider	IEEE Xplore Digital Library
Author	Sherony, M.J. Yang, I.Y. Antoniadis, A. Doyle, B.S.
Copyright Year	1996
Description	Author affiliation: MIT, Cambridge, MA, USA (Sherony, M.J.)
Abstract	SOI MOSFETs fabricated using LOCOS isolation can suffer from source-to-drain leakage along the edge of the silicon island which degrades the subthreshold slope of the device and increases the off-state leakage current. The edge leakage is caused by a parasitic edge transistor in parallel with the main transistor. This leakage is typically more common in NMOS devices because the boron at the tip of the silicon island readily segregates into the surrounding oxide. A technique has been demonstrated which can increase the V/sub T/ of the parasitic edge transistor in LOCOS-isolated NMOS devices, thereby dramatically reducing the parasitic edge leakage without greatly affecting the main transistor. In a research/development environment, this technique offers the possibility of extracting circuit data from a lot whose leakage otherwise prevents meaningful circuit measurement, and thus provides a tool for overcoming parasitic edge leakage without the need to run additional silicon.
Starting Page	84
Ending Page	85
File Size	236823
Page Count	2
File Format	PDF
ISBN	0780333152
ISSN	1078621X
DOI	10.1109/SOI.1996.552505
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-09-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Stress MOS devices Silicon CMOS technology Leakage current Degradation Medical simulation Circuits Boron
Content Type	Text
Resource Type	Article

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