NDLI: Unconventional transistor sizing for reducing power alleviates threshold voltage variations

Content Provider	IEEE Xplore Digital Library
Author	Beg, A. Beiu, V. Ibrahim, W.
Copyright Year	2012
Description	Author affiliation: Faculty of Information Technology, United Arab Emirates University, Al Ain 17551, Abu Dhabi, UAE (Beg, A.; Beiu, V.; Ibrahim, W.)
Abstract	Digital circuits can be synthesized with only NANDs or NORs, while delay and power can be quite different. Scaling transistors increases their sensitivity to variations and in particular to threshold voltage variations (σ). Sizing transistors trades delay versus power, while unconventional sizing (e.g., L > L, W/L < 1, fine-grained increments, multifinger FETs) was proposed recently for reducing power and also σ. Using Monte Carlo simulations we perform an analysis of how sensitive the output voltages of NAND-2 and NOR-2 are to increasing L over L, and examine how such sizing affects delay, power, and power-delay-product of these two gates.
Starting Page	429
Ending Page	432
File Size	804719
Page Count	4
File Format	PDF
ISBN	9781467307376
ISSN	1545857X
e-ISBN	9781467307383
DOI	10.1109/SMICND.2012.6400739
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-15
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates CMOS integrated circuits Reliability Delay Standards Transistors Semiconductor device modeling
Content Type	Text
Resource Type	Article

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Unconventional transistor sizing for reducing power alleviates threshold voltage variations