NDLI: Effect of the process flow on negative-bias-temperature-instability

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2003 8th International Symposium Plasma- and Process-Induced Damage.

2003 8th International Symposium on Plasma- and Process-Induced Damage. (Cat. No.03TH8669)

CMOS downscaling and process induced damages

Critical issues in plasma etching processes involved in the gate etch fabrication of CMOS devices

Interaction between ILD-process and metal-etch induced gate charging effect

Charging damage during contact etch triggered by increased borderless nitride conductivity

Plasma-induced damage on sub-5 nm gate oxide by PECVD-Ti process

Comprehending scaling effects on plasma damage

Systematic deprocessing: a technique for identification of the origins of process-induced damage and threshold voltage shifts

A general concept for monitoring plasma induced charging damage

Physical characterization of ultrathin high k dielectrics

Process induced damage: what challenges lie ahead?

Metal gate and high-k integration for advanced CMOS devices

Plasma-induced charging in two bit per cell SONOS memories

Plasma damage reduction by using ISSG gate oxides

Plasma-induced charge damage and its effect on reliability in 0.115-/spl mu/m technology

Plasma induced substrate damage in high dose implant resist strip process

Impacts of HF etching on ultra-thin core gate oxide integrity in dual gate oxide CMOS technology

Metal contamination monitoring in ion implantation technology

Yield improvement by reducing charge-up damage of double polysilicon capacitors during via etch

Ion orbits in electron shading damage

Gate oxide degradation due to plasma damage related charging while ILD cap oxide deposition - detection, localization and resolution

Prediction of plasma charging damage during SiO/sub 2/ etching by VicAddress

Investigation of gate oxide quality as a function of downstream plasma exposure during flash memory fabrication

A fast plasma induced damage monitoring method

P2ID 2002 industry survey of semiconductor process-induced damage

Survey of semiconductor process-induced damage

Initial gate leakage in ultra thin SiO/sub 2/ - the role of a brief stress

Direct measurement of gate oxide damage from plasma nitridation process

Effects of plasma-induced damage to ultrathin (/spl les/1.5 nm) gate dielectric on equivalent oxide thickness downscaling using plasma nitridation process

Temperature effect on ultra thin SiO/sub 2/ time-dependent-dielectric-breakdown

NBTI in dual gate oxide PMOSFETs

Effect of the process flow on negative-bias-temperature-instability

Effects of gate notching profile defect on characteristic of cell NMOSFET in low-power SRAM device

The effect of fluorine in an advanced CMOS process with triple (1.6/2.2/5.2 nm) nitrided gate oxide

Reduction of plasma-radiation-induced interface states for plasma processes of charge-coupled-device image sensors using pulse-time-modulated plasma

Automated antenna detection and correction methodology in VLSI designs

Process induced damages from various integrated circuit interconnection designs - limitations of antenna rule under practical integrated circuit layout practice

Recent trends in 300-mm plasma equipment

A novel wireless on-wafer plasma sensor using light-emitting diodes

Backend dielectric etch induced wafer arcing mechanism and solution

Investigation of electron-shading effects during high-current ion implants

Low charging damage SiO/sub 2/ etching with a low-angle forward reflected neutral beam

7th International Symposium on Plasma- and Process-Induced Damage

2001 6th International Symposium on Plasma- and Process-Induced Damage (IEEE Cat. No.01TH8538)

2000 5th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.00TH8479)

1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395)

1998 3rd International Symposium on Plasma Process-Induced Damage (Cat. No.98EX100)

2nd International Symposium on Plasma Process-Induced Damage

Proceedings of 1st International Symposium on Plasma Process-Induced Damage

Effect of the process flow on negative-bias-temperature-instability

Content Provider	IEEE Xplore Digital Library
Author	Scarpa, A. van Marwijk, L. Cacciato, A. Ballarin, F.
Copyright Year	2003
Description	Author affiliation: Philips Semicond., Nijmegen, Netherlands (Scarpa, A.; van Marwijk, L.; Cacciato, A.; Ballarin, F.)
Abstract	PMOSFET parametric degradation during negative-bias high temperature aging can depend on many steps of the manufacturing process flow. The effect of some process steps on NBTI is discussed with a phenomenological approach. In particular, we report a case in which plasma induced charging reduces the PMOSFET instability.
Sponsorship	IEEE/Electron Devices Soc. Japanese Soc. Appl. Phys
Starting Page	142
Ending Page	145
File Size	373811
Page Count	4
File Format	PDF
ISBN	0780377478
DOI	10.1109/PPID.2003.1200943
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-04-24
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Niobium compounds Titanium compounds MOSFET circuits Stress Degradation Manufacturing processes Threshold voltage Modems Plasma temperature Negative bias temperature instability
Content Type	Text
Resource Type	Article

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