NDLI: Comparison between random and pseudo-random generation for BIST of delay, stuck-at and bridging faults

Content Provider	IEEE Xplore Digital Library
Author	Girard, P. Landrault, C. Pravossoudovitch, S. Virazel, A.
Copyright Year	2000
Description	Author affiliation: Lab. d'Inf., de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France (Girard, P.)
Abstract	The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost. The generation of test patterns in this case is usually pseudo-random (produced from an LFSR), and it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this paper, we first question the use of a pseudo-random generation to produce effective delay test pairs. We demonstrate that using truly random test pairs (produced from a software generation) to test path delay faults in a given circuit produces higher delay fault coverage than that obtained with pseudo-random test pairs obtained from a classical primitive LFSR. Next, we show that the same conclusion can be drawn when stuck-at or bridging fault coverage is targeted rather delay fault coverage. A modified hardware TPG structure allowing the generation of truly random test patterns is introduced at the end of the paper.
Starting Page	121
Ending Page	126
File Size	212017
Page Count	6
File Format	PDF
ISBN	0769506461
DOI	10.1109/OLT.2000.856623
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-07-03
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Circuit testing Circuit faults Automatic testing Software testing Test pattern generators Delay effects Very large scale integration Costs Silicon carbide
Content Type	Text
Resource Type	Article

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