NDLI: A novel on-chip delay measurement hardware for efficient speed-binning

Content Provider	IEEE Xplore Digital Library
Author	Raychowdhury, A. Ghosh, S. Roy, K.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA (Raychowdhury, A.; Ghosh, S.; Roy, K.)
Abstract	With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spectrum. Consequently, speed binning of the high performance VLSI chips is essential and it costs significant amount of test application time. Further, the knowledge of the actual delay in the critical path of the circuit enables efficient use of typical low power methodologies e.g., voltage scaling, adaptive body biasing etc. In this paper, the authors have proposed a novel on-chip, low overhead and process tolerant delay measurement circuit which can estimate the critical path delay in a single clock period. This has the advantage of efficient on-chip speed binning.
Starting Page	287
Ending Page	292
File Size	727391
Page Count	6
File Format	PDF
ISBN	0769524060
DOI	10.1109/IOLTS.2005.10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-07-06
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Velocity measurement Hardware Delay estimation CMOS technology Semiconductor device measurement Threshold voltage Very large scale integration Costs Circuit testing Clocks process variation Speed binning delay measurement hardware
Content Type	Text
Learning Resource Type	Article

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