NDLI: Concurrent error detection in sequential circuits implemented using FPGAs with embedded memory blocks

Content Provider	IEEE Xplore Digital Library
Author	Krasniewski, A.
Copyright Year	2004
Description	Author affiliation: Inst. of Telecommun., Warsaw Univ. of Technol., Poland (Krasniewski, A.)
Abstract	We propose a low-overhead concurrent error detection scheme for a sequential circuit implemented using an FPGA with embedded memory blocks (EMBs). The presented scheme is proven to detect each permanent or transient fault associated with a single input or output of any component of the circuit that leads to an incorrect state transition. Such faults are detected with no latency. Our technique requires significantly less extra logic than the earlier proposed schemes for concurrent error detection in sequential circuits. For a large percentage of the examined benchmark circuits, no extra EMBs and just 3 extra LUTs are needed; for other circuits, the number of extra EMBs is quite limited - on average, an overhead in terms of the number of EMBs is 13.6%.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	67
Ending Page	72
File Size	291034
Page Count	6
File Format	PDF
ISBN	0769521800
DOI	10.1109/OLT.2004.1319661
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-07-14
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sequential circuits Field programmable gate arrays Circuit faults Programmable logic arrays Electrical fault detection Fault detection Logic devices Registers Table lookup Random access memory
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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