NDLI: A multichannel TDC based on ring-delay time multiplexer: A prototype

Content Provider	IEEE Xplore Digital Library
Author	Bocci, V. lacoangeli, F. Nobrega, R.
Copyright Year	2007
Abstract	We have designed and implemented on a Xilinx Spartan HE FPGA a highly integrated time-multiplexing device by means of using a ring-delay loop. This idea grow out of Time Multiplexer introduced in NSS-2005 conference at Puertorico[l]. Single ring-delay is designed as a simple fixed loop delay by feedback. A 4+4 bit input value allows fixing the delay time amount as number of loop delay cycle: first 4 bit holds delay time of all input signal and second marks the output delay-slot. Different input signals are putted into as many delay-ring everyone with different value of 4 bit delay slot number. So, several channels can be merged into one channel delayed with different time, 150ns incremented. As a consequence, usage of one multi-hit channel to measure timing of up to 16 channels is possible if low rate of input signal is foreseen. Timing measurements show a max RMS jitter, for 16 ring-delay cycle, lower than 1 ns for about 2,4 mus of time delay, likely a passable contribution to timing misalignments.
Starting Page	720
Ending Page	724
File Size	922520
Page Count	5
File Format	PDF
ISBN	9781424409228
ISSN	10957863
DOI	10.1109/NSSMIC.2007.4436433
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Prototypes Delay effects Field programmable gate arrays Time measurement Circuits Timing jitter Cables Delay lines Semiconductor device measurement
Content Type	Text
Learning Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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