NDLI: Using multiple FPGA architectures for real-time processing of low-level machine vision functions

Content Provider	IEEE Xplore Digital Library
Author	Drayer, T.H. King IV, W.E. Tront, J.G. Conners, R.W. Araman, P.A.
Copyright Year	1995
Description	Author affiliation: Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA (Drayer, T.H.; King, W.E., IV; Tront, J.G.; Conners, R.W.)
Abstract	In this paper, we investigate the use of multiple field programmable gate array (FPGA) architectures for real-time machine vision processing. The use of FPGAs for low level processing represents an excellent tradeoff between software and special purpose hardware implementations. A library of modules that implement common low-level machine vision operations is presented. These modules are designed with gate-level hardware components that are compiled into the functionality of the FPGA chips. A common input/output interface is created for use in each of the modules, allowing the interconnection of several image processing modules in a parallel or pipelined manner. This new synchronous, unidirectional interface establishes a protocol for the transfer of image and result data between modules. This reduces the design complexity and allows several different low-level operations to be applied to the same input image. A method is developed to partition and compile the design into the hardware resources of multiple FPGA chips. Experimental results verify the efficiency of using common multiple FPGA architectures to implement real-time machine vision processing.
Starting Page	1284
Ending Page	1289
File Size	671019
Page Count	6
File Format	PDF
ISBN	0780330269
DOI	10.1109/IECON.1995.483982
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-11-06
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Machine vision Hardware Programmable logic arrays Logic arrays Computer architecture Image processing Signal generators Random access memory Real time systems
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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