NDLI: Alignability equivalence of synchronous sequential circuits

Content Provider	IEEE Xplore Digital Library
Author	Rosenmann, A. Hanna, Z.
Copyright Year	2002
Description	Author affiliation: Dept. of Logic & Validation Technol., Intel, Haifa, Israel (Rosenmann, A.; Hanna, Z.)
Abstract	Sequential verification is a well known research framework that has attracted many researchers in the aca demic and industrial worlds during the last few decades. In this framework, initialization of synchronous models is one of the fundamental and challenging research topics that is difficult to solve, especially when talking about large industrial strengths hardware models. Many researchers in this domain such as Pomeranz and Reddy (1994), Pixley and Beihl (1991), and Pixley, Jeong and Hachtel (1994), and others tried to analyze and propose solutions to this problem, however the majority of the approaches used were based on BDDs and classical reachability analysis methods, which by nature suffer from capacity and complexity limits. When talking about hardware formal equivalence verification, the Initialization issue becomes even more complex especially when trying to verify the logic equivalence of two large industrial circuits. In this note we propose a new adaptive and iterative approach that combines various symbolic simulation techniques and bounded model checking algorithms to initialize sequential circuits for the alignability equivalence verification. The novelty of our method has been employed on complex real life sequential models from Intel lead Pentium processor designs. These methods are already implemented in Intel's sequential verification engine, Insight.
Sponsorship	IEEE Comput. Soc. Tech. Council on Test Technol. IEEE Comput. Soc. Tech. Committee on Design Autom
Starting Page	111
Ending Page	114
File Size	383004
Page Count	4
File Format	PDF
ISBN	0780376552
DOI	10.1109/HLDVT.2002.1224438
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-10-29
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sequential circuits Hardware Data structures Boolean functions Reachability analysis Logic circuits Iterative methods Circuit simulation Iterative algorithms Process design
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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