NDLI: A Simple BSP-based Model to Predict Execution Time in GPU Applications

Content Provider	IEEE Xplore Digital Library
Author	Amaris, M. Cordeiro, D. Goldman, A. De Camargo, R.Y.
Copyright Year	2015
Description	Author affiliation: Dept. of Comput. Sci., Fed. Univ. of ABC, Santo Andre, Brazil (De Camargo, R.Y.) \|\| Inst. of Math. & Stat., Univ. of Sao Paulo, Sao Paulo, Brazil (Amaris, M.; Cordeiro, D.; Goldman, A.)
Abstract	Models are useful to represent abstractions of software and hardware processes. The Bulk Synchronous Parallel (BSP) is a bridging model for parallel computation that allows algorithmic analysis of programs on parallel computers using performance modeling. The main idea of BSP model is the treatment of communication and computation as abstractions of a parallel system. Meanwhile, the use of GPU devices are becoming more widespread and they are currently capable of performing efficient parallel computation for applications that can be decomposed on thousands of simple threads. However, few models for predicting application execution time on GPUs have been proposed. In this work we present a simple and intuitive BSP-based model for predicting the CUDA application execution times on GPUs. The model is based on the number of computations and memory accesses of the GPU, with additional information on cache usage obtained from profiling. Scalability, divergence, effect of optimizations and differences of architectures are adjusted by a single parameter. We evaluated our model using two applications and six different boards. We showed by using profile information for a single board, that the model is general enough to predict the execution time of an application with different input sizes and on different boards with the same architecture. Our model predictions were within 0.8 to 1.2 times the measured execution times, which are reasonable for such a simple model. These results indicate that the model is good enough to generalize the predictions for different problem sizes and GPU configurations.
Starting Page	285
Ending Page	294
File Size	1996229
Page Count	10
File Format	PDF
e-ISBN	9781467384889
DOI	10.1109/HiPC.2015.34
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-16
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational modeling Graphics processing units Computer architecture Instruction sets Predictive models Kernel CUDA BSP model Performance Prediction GPGPU Kepler Architecture
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Performance modeling in CUDA streams — A means for high-throughput data processing

Performance comparison of CPU and GPU on a discrete heterogeneous architecture

Barra: A Parallel Functional Simulator for GPGPU

Nuclear Fusion Simulation Code Optimization and Performance Evaluation on GPU Cluster

High performance computing and simulations on the GPU using CUDA

A Translation Framework for Virtual Execution Environment on CPU/GPU Architecture

BFS-4K: An Efficient Implementation of BFS for Kepler GPU Architectures

A GPU-based Implementation of WRF PBL/MYNN Surface Layer Scheme

Parallelism of Clonal Selection for PSP on CUDA

A Simple BSP-based Model to Predict Execution Time in GPU Applications

Similar Documents

Performance modeling in CUDA streams — A means for high-throughput data processing

Performance comparison of CPU and GPU on a discrete heterogeneous architecture

Barra: A Parallel Functional Simulator for GPGPU

Nuclear Fusion Simulation Code Optimization and Performance Evaluation on GPU Cluster

High performance computing and simulations on the GPU using CUDA

A Translation Framework for Virtual Execution Environment on CPU/GPU Architecture

BFS-4K: An Efficient Implementation of BFS for Kepler GPU Architectures

A GPU-based Implementation of WRF PBL/MYNN Surface Layer Scheme

Parallelism of Clonal Selection for PSP on CUDA

A Simple BSP-based Model to Predict Execution Time in GPU Applications