NDLI: Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures

Content Provider	IEEE Xplore Digital Library
Author	Noguera, J. Badia, R.M.
Copyright Year	2002
Abstract	Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreover, dynamically reconfigurable logic (DRL) architectures are an exciting alternative for embedded systems design. However, all previous approaches to DRL multi-context scheduling and HW/SW scheduling for DRL architectures are based on static scheduling techniques. In this paper, we address this problem and present: (1) a dynamic scheduler hardware architecture, and (2) four dynamic run-time scheduling algorithms for DRL-based multi-context platforms. The scheduling algorithms have been integrated in our codesign environment, where a large number of experiments have been carried out. Results demonstrate the benefits of our approach.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Design Autom. IEEE Comput. Soc. Tech. Council on Software Eng. IEEE Circuits & Syst. Soc. IFIP WG 10.5 ACM SIG Software Eng. ACM SIG Design Autom
Starting Page	205
Ending Page	210
File Size	479353
Page Count	6
File Format	PDF
ISBN	1581135424
DOI	10.1109/CODES.2002.1003626
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Runtime Dynamic scheduling Reconfigurable architectures Reconfigurable logic Embedded system Application software Scheduling algorithm Programmable logic arrays Programmable logic devices System-on-a-chip
Content Type	Text
Resource Type	Article

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