NDLI: Design of a SOI memory cell

Content Provider	IEEE Xplore Digital Library
Author	Stanojevic, Z. Ioannou, D.E. Loncar, B. Osmokrovic, P.
Copyright Year	1997
Abstract	In this paper a quantitative analysis has been used for describing and discussing design characterizations of an SOI flash memory cell. Mathematical expressions for the front gate threshold voltage of the SOI memory cell are derived using the equations for a standard SOI MOSFET. Coupling coefficients which exist between the control gate and source and drain regions, are the same as for the silicon body, through stored charge at the floating gate has to be included in these equations and the mathematical expressions for the flash memory cell can be obtained. Implementing this, the voltage of the front gate of a standard SOI MOSFET is equal to the voltage of the floating gate of the memory cell. During analysis, the emphasis is put on the case where the back channel is depleted, because then coupling between the front and back gate can control the threshold voltage of the control gate.
Starting Page	297
Ending Page	300
File Size	380222
Page Count	4
File Format	PDF
ISBN	078033664X
DOI	10.1109/ICMEL.1997.625255
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-09-14
Publisher Place	Yugoslavia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nonvolatile memory Silicon on insulator technology Threshold voltage Voltage control Equations Flash memory cells MOSFET circuits Insulation Parasitic capacitance Silicon compounds
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Opposite side floating gate SOI FLASH memory cell

One application of SOI memory cell-memory array

Short channel effect of SOI vertical sidewall MOSFET

Channel design of silicon-on-insulator (SOI) MOSFET for low-voltage low-power application

Novel SOI CMOS design using ultra thin near intrinsic substrate

Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's

Investigation of Gate Length Effect on SOI-MOSFET Operation

Simulation of Program Characteristics of Nanocrystal Flash Memory Devices

Novel 3D SOI RF power MOSFET

Design of a SOI memory cell

Similar Documents

Opposite side floating gate SOI FLASH memory cell

One application of SOI memory cell-memory array

Short channel effect of SOI vertical sidewall MOSFET

Channel design of silicon-on-insulator (SOI) MOSFET for low-voltage low-power application

Novel SOI CMOS design using ultra thin near intrinsic substrate

Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's

Investigation of Gate Length Effect on SOI-MOSFET Operation

Simulation of Program Characteristics of Nanocrystal Flash Memory Devices

Novel 3D SOI RF power MOSFET

Design of a SOI memory cell