NDLI: Fast error-correcting circuits for fault-tolerant memory

Content Provider	IEEE Xplore Digital Library
Author	Ou, E. Yang, W.
Copyright Year	2004
Description	Author affiliation: VLSI Group, Harvard Univ., Cambridge, MA, USA (Ou, E.; Yang, W.)
Abstract	This work explores the design and analysis of an error-correcting circuit as applied to high density and low latency memories, especially NOR Flash and DRAM. In very high density semiconductor memory products, exhaustive testing and repair procedures are essential to insure the proper operation of every memory location under worst possible conditions and can account for a significant portion of the total production cost. The implementation of error-correcting circuits in conjunction with other currently-used methods for designing more fault-tolerant high density memory could allow for more simplified testing procedures after memory fabrication and significantly reduce the overall cost. Also, error-correcting circuits could increase the reliability of the memory and extend its lifetime. This paper illustrates one possible implementation of error-correcting circuits, in the form of a Hamming decoder. Clocking was accomplished with asynchronous pulse generators to ensure fast cycle times and minimal decoding delay. These circuits were designed to show that error correction can be achieved with minimal additional circuitry, system complexity, power consumption and latency.
Starting Page	8
Ending Page	12
File Size	297397
Page Count	5
File Format	PDF
ISBN	0769521932
ISSN	10874852
DOI	10.1109/MTDT.2004.1327977
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Delay Circuit testing Costs Decoding Error analysis Random access memory Semiconductor memory Semiconductor device testing Production
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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