NDLI: Gated low-power clock tree synthesis for 3D-ICs

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2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

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Gated low-power clock tree synthesis for 3D-ICs

Content Provider	IEEE Xplore Digital Library
Author	Tiantao Lu Srivastava, A.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Maryland, College Park, MD, USA (Tiantao Lu; Srivastava, A.)
Abstract	In this paper, we minimize 3D clock power using shutdown gates to selectively turn off unnecessary clock activities. In 3D-IC, shutdown signals require large-sized Through-Silicon-Vias(TSVs), so we propose a simulated annealing(SA) based algorithm along with a force-directed TSV placer to decide the selection of shutdown gates and the locations of TSVs under layout whitespace constraint. Furthermore, we recognize optimal power saving is achieved when the clock tree itself is designed simultaneously with the shutdown network. Experimental results show that our heuristic decreases the total clock power by more than 20% with less than 1.5% wirelength overhead while ensuring zero clock skew.
Starting Page	319
Ending Page	322
File Size	415051
Page Count	4
File Format	PDF
DOI	10.1145/2627369.2627665
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Clocks Through-silicon vias Logic gates Three-dimensional displays Wires Layout Synchronization optimization 3D-ICs TSV clock gating
Content Type	Text
Resource Type	Article

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