NDLI: Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI

Content Provider	IEEE Xplore Digital Library
Author	Yiran Chen Hai Li Jing Li Cheng-Kok Koh
Copyright Year	2007
Description	Author affiliation: Seagate Technol., Bloomington, MN, USA (Yiran Chen; Hai Li) \|\| Purdue Univ., West Lafayette, IN, USA (Jing Li; Cheng-Kok Koh)
Abstract	Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) technique for NBTI tolerance. By detecting the circuit failure on-the-fly, the proposed VL-adder can automatically shift data capturing clock edge to tolerate NBTI-induced delay degradation on critical timing paths. VL-adder operates with a fixed supply voltage and clock period, avoiding the high design and manufacturing costs incurred by existing NBTI-tolerant techniques. Compared to other related lower-power adder designs, VL-adder technique always provides better energy efficiency through the whole chip lifetime with very limited performance degradation (4.6% or less).
Starting Page	195
Ending Page	200
File Size	264539
Page Count	6
File Format	PDF
ISBN	9781595937094
DOI	10.1145/1283780.1283822
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Adders Arithmetic Circuit synthesis Niobium compounds Titanium compounds Clocks Degradation Negative bias temperature instability MOSFETs Delay variable-latency adder (VL-adder) negative bias temperature instability (NBTI)
Content Type	Text
Resource Type	Article

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