NDLI: An energy efficient TLB design methodology

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2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

International Symposium on Low Power Electronics and Design (ISLPED)

IEEE/ACM International Symposium on Low Power Electronics and Design

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED)

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design (IEEE Cat. No. 05TH8842)

ISLPED'05 Proceedings of the 2005 International Symposium on Low Power Electronics and Design

Table of contents

ISLPED 2005 Executive Committee and Symposium Officers

Technology and design challenges for mobile communication and computing products

FinFET-based SRAM design

Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits

Effectiveness of low power dual-V/sub t/ designs in nano-scale technologies under process parameter variations

Analysis and mitigation of variability in subthreshold design

Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

Instruction packing: reducing power and delay of the dynamic scheduling logic

Energy-efficient and high-performance instruction fetch using a block-aware ISA

Energy-aware fetch mechanism: trace cache and BTB customization

Understanding the energy efficiency of SMT and CMP with multiclustering

A simple mechanism to adapt leakage-control policies to temperature

A 120nm low power asynchronous ADC

A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13/spl mu/m CMOS

A low power current steering digital to analog converter in 0.18 micron CMOS

Systematic power reduction and performance analysis of mismatch limited ADC designs

A novel predictive inductor multiplier for integrated circuit DC-DC converters in portable applications

Challenges and opportunities for low power FPGAs in nanometer technologies [Special Session]

A GHz-class charge recovery logic

Low-power fanout optimization using multiple threshold voltage inverters

A low-power bus design using joint repeater insertion and coding

An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS

A low-power, multichannel gated oscillator-based CDR for short-haul applications

An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs

Cascaded carry-select adder (C/sup 2/SA): a new structure for low-power CSA design

Region-level approximate computation reuse for power reduction in multimedia applications

Joint exploration of architectural and physical design spaces with thermal consideration

Coordinated, distributed, formal energy management of chip multiprocessors

A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations

Power-optimal repeater insertion considering V/sub dd/ and V/sub th/ as design freedoms

Probabilistic dual-Vth leakage optimization under variability

Linear programming for sizing, V/sub th/ and V/sub dd/ assignment

An efficient (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design

Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications

Two efficient methods to reduce power and testing time

Power and thermal effects of SRAM vs. latch-mux design styles and clock gating choices

Platform trends for the digital home and enterprise [Plenary Talk]

Complexity reduction in an nRERL microprocessor

Driver pre-emphasis techniques for on-chip global buses

Multi-story power delivery for supply noise reduction and low voltage operation

Low power SRAM techniques for handheld products

High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar

An evaluation of code and data optimizations in the context of disk power reduction

Optimizing sensor movement planning for energy efficiency

Power prediction for Intel XScale/spl reg/ processors using performance monitoring unit events

Power reduction by varying sampling rate

Energy efficient strategies for deployment of a two-level wireless sensor network

Power grid voltage integrity verification

The need for a full-chip and package thermal model for thermally optimized IC designs

Peak temperature control and leakage reduction during binding in high level synthesis

LAP: a logic activity packing methodology for leakage power-tolerant FPGAs

Defocus-aware leakage estimation and control

Hierarchical power management with application to scheduling

Runtime identification of microprocessor energy saving opportunities

Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy

Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation

Power-aware code scheduling for clusters of active disks

Design Contest Presentations

Hot topic: low power multi-core architectures [Special Session]

Low-power ultra-wideband (UWB) transceiver design [Special Session]

Wearable computing - a catalyst for business and entertainment

Design and optimization on dynamic power system for self-powered integrated wireless sensing nodes

Accurate battery lifetime estimation using high-frequency power profile emulation

On-chip digital power supply control for system-on-chip applications

Self-timed circuits for energy harvesting AC power supplies

A tunable bus encoder for off-chip data buses

Fast configurable-cache tuning with a unified second-level cache

Dataflow analysis for energy-efficient scratch-pad memory management

Energy reduction in multiprocessor systems using transactional memory

Inter-program optimizations for conserving disk energy

PARE: a power-aware hardware data prefetching engine

Snug set-associative caches. Reducing leakage power while improving performance

An energy efficient TLB design methodology

Synonymous address compaction for energy reduction in data TLB

A non-uniform cache architecture for low power system design

Replacing global wires with an on-chip network: a power analysis

A low-power crossroad switch architecture and its core placement for network-on-chip

System level power and performance modeling of GALS point-to-point communication interfaces

A technique for low energy mapping and routing in network-on-chip architectures

Improving energy efficiency by making DRAM less randomly accessed

Notes [blank pages]

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.

Proceedings of the International Symposium on Low Power Electronics and Design

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581)

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379)

Proceedings of 1997 International Symposium on Low Power Electronics and Design

Proceedings of 1996 International Symposium on Low Power Electronics and Design

An energy efficient TLB design methodology

Content Provider	IEEE Xplore Digital Library
Author	Dongrui Fan Zhimin Tang Hailin Huang Gao, G.R.
Copyright Year	2005
Description	Author affiliation: Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China (Dongrui Fan; Zhimin Tang; Hailin Huang)
Abstract	This paper researches translation look-aside buffer (TLB) of embedded processor. Based on an analysis of design-related factors: power, area, critical path and performance of the research model - Godson-I, a low-power TLB design is proposed without sacrifice of performance and timing. Using this method, the following results are achieved: power of TLB-RAM reduces 92.7% and area of TLB-RAM reduces 50%. Compared with other methods, the hit rate of this design is much higher and the accessing conflict to RAM between ITLB and DTLB is much reduced. Although our work targets to Godson-I, the proposed methodology should be applicable to other designs.
Sponsorship	ACM SIGDA IEEE Circuits and Syst. Soc
Starting Page	351
Ending Page	356
File Size	953506
Page Count	6
File Format	PDF
ISBN	1595931376
DOI	10.1109/LPE.2005.195546
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Energy efficiency Design methodology Read-write memory Timing Process design Energy consumption Telephony Performance analysis Permission Embedded computing
Content Type	Text
Resource Type	Article

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