NDLI: Low power high level synthesis by increasing data correlation

Content Provider	IEEE Xplore Digital Library
Author	Dongwan Shin Kiyoung Choi
Copyright Year	1997
Description	Author affiliation: Sch. of Electr. Eng., Seoul Nat. Univ., South Korea (Dongwan Shin)
Abstract	With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an important issue in the design of electronic systems. Low power design techniques have been pursued at all design levels. However, it is more effective to attempt to reduce power dissipation at higher levels of abstraction which allows a wider view. In this paper, we propose a simultaneous scheduling and binding scheme which increases the correlation between consecutive inputs to an execution unit so that the switched capacitance of the execution unit is reduced. The proposed method is implemented and integrated into the scheduling and assignment part of the HYPER synthesis environment. Compared with the original HYPER synthesis system, average power saving of 23.0% in execution units and 14.2% in the whole circuit, is obtained for a set of benchmark examples.
Starting Page	62
Ending Page	67
File Size	571965
Page Count	6
File Format	PDF
ISBN	0897919033
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-08-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	High level synthesis Energy consumption Capacitance Circuits Voltage Permission Very large scale integration Processor scheduling Power dissipation Optimization
Content Type	Text
Resource Type	Article

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