NDLI: Gate-level synthesis for low-power using new transformations

Please wait, while we are loading the content...

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

International Symposium on Low Power Electronics and Design (ISLPED)

IEEE/ACM International Symposium on Low Power Electronics and Design

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED)

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.

Proceedings of the International Symposium on Low Power Electronics and Design

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581)

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379)

Proceedings of 1997 International Symposium on Low Power Electronics and Design

Proceedings of 1996 International Symposium on Low Power Electronics and Design

Proceedings of 1996 International Symposium on Low Power Electronics and Design

The design of a high performance low power microprocessor

Low power systems for wireless microsensors

A low power architecture for wireless multimedia systems: lessons learned from building a power hog

High-level power estimation

A power metric for mobile systems

Lower bounds on power-dissipation for DSP algorithms

A 0.5 V/100 MHz over-V/sub CC/ grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes

Energy recovery for the design of high-speed, low-power static RAMs

A 1-V 1-Mb SRAM for portable equipment

A novel methodology for transistor-level power estimation [CMOS circuits]

Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques

Switching activity analysis for sequential circuits using Boolean approximation method

Transition reduction in carry-save adder trees

250-600 MHz 12b digital filters in 0.8-0.25 /spl mu/m bulk and SOI CMOS technologies

A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element

Design techniques for high-performance, energy-efficient control logic

Energy-recovery CMOS for highly pipelined DSP designs

A sub-CV/sup 2/ pad driver with 10 ns transition time

Gate-level current waveform simulation of CMOS integrated circuits

Effects of correlations on accuracy of power analysis-an experimental study

Basic experimentation on accuracy of power estimation for CMOS VLSI circuits

Simulation based architectural power estimation for PLA-based controllers

Short circuit power consumption of glitches

A graded-channel MOS (GCMOS) VLSI technology for low power DSP applications

Fabrication and performance of mesa interconnect

Floating body effects in partially-depleted SOI CMOS circuits

An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits

Concurrency-oriented optimization for low-power asynchronous systems

Energy minimization using multiple supply voltages

Symbolic computation of logic implications for technology-dependent low-power synthesis

Integrated resynthesis for low power

How to design low-power digital cellular phones

What is the state of the art in commercial EDA tools for low power?

Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices

Circuit techniques for low power CMOS GSI

Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models

Energy delay analysis of partial product reduction methods for parallel multiplier implementation

Low-power radix-4 divider

Power comparisons for barrel shifters

Interlaced accumulation programming for low power DSP

Low-power adaptive filter architectures via strength reduction

Leap frog multiplier

Manufacturability of low power CMOS technology solutions

Effects of random MOSFET parameter fluctuations on total power consumption

The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits

12-b 125 MSPS CMOS D/A designed for spectral performance

Implementation of a micro power 15-bit 'floating-point' A/D converter

Micro power "relative precision" 13 bits cyclic RSD A/D converter

Fixed-phase retiming for low power design

Clock-skew optimization for peak current reduction

Simultaneous buffer and wire sizing for performance and power optimization

A low power high performance switched-current multiplier

Low-power frequency multiplier with one cycle lock-in time and 100 ppm frequency resolution, for system power-management

A 1.5 V class AB output buffer

Low power mapping of behavioral arrays to multiple memories

Logic synthesis using power-sensitive Don't Care sets

Gate-level synthesis for low-power using new transformations

Controller re-specification to minimize switching activity in controller/data path circuits

A 200 /spl mu/A, 78 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppm

Substrate noise influence on circuit performance in variable threshold-voltage scheme

A low power switching power supply for self-clocked systems

Design of a programmable temperature monitoring device for tagging small fish

Entropic bounds on FSM switching

High-level power estimation and the area complexity of Boolean functions

Two-dimensional codes for low power

Low power, testable dual edge triggered flip-flops

Data driven signal processing: an approach for energy efficient computing

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer

Power exploration for data dominated video applications

Practical performance/power alternatives within an existing CMOS technology generation

A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI)

Comparison of high speed voltage-scaled conventional and adiabatic circuits

Static power driven voltage scaling and delay driven buffer sizing in Mixed Swing QuadRail for sub-1 V I/O swings

Gate-level synthesis for low-power using new transformations

Content Provider	IEEE Xplore Digital Library
Author	Pradhan, D.K. Chatterjee, M. Swarna, M.V. Kunz, W.
Copyright Year	1996
Description	Author affiliation: Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA (Pradhan, D.K.)
Abstract	A new logic optimization method of multi-level combinational CMOS circuits is presented, which minimizes both power as well as power dissipation per unit area. The method described here uses Boolean transformations which exploit implications at the gate-level, based on both controllability and observability relationships. New transformations which form the basis of our synthesis method are presented. The emphasis is on power consumption rather than on area. Experimental results demonstrate that circuits synthesized by our method consume less power with a comparable area than those synthesized by state-of-the-art tools.
Starting Page	297
Ending Page	300
File Size	520946
Page Count	4
File Format	PDF
ISBN	0780335716
DOI	10.1109/LPE.1996.547527
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-08-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cost function Circuit synthesis Capacitance Energy consumption CMOS logic circuits Optimization methods CMOS digital integrated circuits Power dissipation Network synthesis Kernel
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in