NDLI: FPGA-based test bed for design and evaluation of low-power FIR-filter hardware accelerators

Content Provider	IEEE Xplore Digital Library
Author	Walters, E.G. Arner, J.J. Rojahn, N.D.
Copyright Year	2012
Description	Author affiliation: Penn State Erie, The Behrend College, Erie, PA, USA (Walters, E.G.; Arner, J.J.; Rojahn, N.D.)
Abstract	Finite impulse response (FIR) filters are often used for processing audio, communication and other signals. Truncated-matrix multipliers offer reduced area, power and delay at the expense of increased computational error. This paper describes a test bed for low-power FIR-filter hardware accelerators that use truncated-matrix multipliers. It accepts analog input signals, filters them in real-time using an inexpensive field-programmable gate array (FPGA) development board, and produces analog outputs. The input is simultaneously processed using truncated-matrix multipliers and standard multipliers for comparison. Parameters such as filter coefficients, the number of unformed columns and the error correction method can be changed on the fly. The test bed enables real-time testing at the systems-integration level using real analog inputs and outputs.
Starting Page	1
Ending Page	4
File Size	297996
Page Count	4
File Format	PDF
ISBN	9781467313544
ISSN	21591423
e-ISBN	9781467313568
DOI	10.1109/ISCE.2012.6241684
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filter Field programmable gate arrays Standards Registers Logic gates Very large scale integration Digital signal processing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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