NDLI: 3D simulation of charge collection and SEU of 0.13µm partially depleted SOI SRAM

Content Provider	IEEE Xplore Digital Library
Author	Xiaochen Zhang Suge Yue Liang Wang Jiancheng Li
Copyright Year	2010
Description	Author affiliation: Beijing Microelectronics Technology Institute, 2 Siyingmen North Road, Fengtai District, 100076, China (Xiaochen Zhang; Suge Yue; Liang Wang; Jiancheng Li)
Abstract	In this paper, the charge collection and parasitic bipolar effect of SOI NMOS devices in case of different ion strike locations have been analyzed through 3D simulation. The simulation results show that the strike at drain region can cause charge collection comparable with the collection induced by strike at the gate region above body. Single event upset (SEU) simulations of SRAM cell have been conducted. Results indicate that the reverse-biased drain region is sensitive to SEU, as well as the gate region. The largest amount of charge collection in device and the lowest LET threshold of SEU in SRAM both occur when the ion strikes at the drain/body junction area and passes through the centre part of the reverse junction.
Starting Page	149
Ending Page	152
File Size	482869
Page Count	4
File Format	PDF
ISBN	9781424485215
ISSN	19308841
e-ISBN	9781424485246
DOI	10.1109/IIRW.2010.5706511
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Single event upset Random access memory Electric potential Silicon Junctions Silicon on insulator technology
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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3D simulation of charge collection and SEU of 0.13µm partially depleted SOI SRAM

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